TNETV1647GSTZWT datasheet(111/236 Pages) TI1

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TMS320DM6441

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SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

Table 6-13. PLLC1 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

At 1.05-V CVDD

400

405

MHz

PLLOUT

At 1.2-V CVDD

400

513

MHz

At 1.05-V CVDD

405

MHz

SYSCLK1 (CLKDIV1 Domain)

At 1.2-V CVDD

513

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Table 6-14. PLLC2 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

At 1.05-V CVDD

400

600

MHz

PLLOUT

At 1.2-V CVDD

400

900

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0

transition). The PLL should not be operated until this stabilization time has expired. This stabilization step

must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the

PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-15.

The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0)

before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-15.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1

with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the

PLL lock time value, see Table 6-15.

Table 6-15. PLL1 and PLL2 Stabilization, Lock, and Reset Times

PLL STABILIZATION/LOCK/RESET TIME

MIN

TYP

MAX

UNIT

PLL Stabilization Time

150

PLL Lock Time

2000C(1)

PLL Reset Time

128C(1)

(1)

C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.

For details on the PLL initialization software sequence, see the TMS320DM644x DMSoC ARM Subsystem

Reference Guide (literature number SPRUE14).

6.6.2

Clock PLL Considerations with External Clock Sources

If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power

both the DM6441 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times

should also be observed. For the input clock timing requirements, see Section 6.6.3, Clock PLL Electrical

Data/Timing (Input and Output Clocks).

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature and Section 6.6.3,

Clock PLL Electrical Data/Timing (Input and Output Clocks).

Peripheral and Electrical Specifications

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