TNETV1647GSTZWT datasheet(115/236 Pages) TI1

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TMS320DM6441

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SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

6.7

Interrupts

The DM6441 device has a large number of interrupts to service the needs of its many peripherals and

subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device

interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt

controller. The interrupts can be selectively enabled or disabled in either of the controllers. In typical

applications, the ARM handles most of the peripheral interrupts and grants control, to the C64x+, of

interrupts that are relevant to DSP algorithms. Also, the ARM and DSP can communicate with each other

through interrupts.

6.7.1

ARM CPU Interrupts

The ARM9 CPU core supports two direct interrupts: FIQ and IRQ. The DM6441 ARM interrupt controller

prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed in

Table 6-20, and interrupts the ARM CPU. Each interrupt is programmable for up to eight levels of priority.

There are six levels for IRQ and two levels for FIQ. Interrupts at the same priority level are serviced in

order by the ARM Interrupt Number, with the lowest number having the highest priority. Table 6-21 shows

the ARM interrupt controller registers and memory locations. For more details on ARM interrupt control,

see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

Peripheral and Electrical Specifications

115

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TNETV1647GSTZWT Datasheet(PDF) 115 Page - Texas Instruments