TNETV1647GSTZWT datasheet(110/236 Pages) TI1

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PLLV

DD18

EMIFilter

+1.8V

DM644x

PLL2

PLL1

0.1µF

0.01µF

TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

Table 6-12. PLL and Reset Controller Registers Memory Map (continued)

HEX ADDRESS RANGE

DESCRIPTION

0x01C4 0D50

SYSTAT

PLL Controller 2 System Clock Status 1 Register (Indicates SYSCLK on/off

Status)

6.6.1

PLL1 and PLL2

Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLLVDD18). It is

recommended that an external EMI filter circuit be added to PLLVDD18, as shown in Figure 6-13. The 1.8-V

supply of the EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O

power-supply

pins

(DVDD).

recommends

EMI

filter

manufacturer

Murata,

part

number

NFM18CC222R1C3.

All PLL external components (C1, C2, and the EMI Filter) should be placed as close to the device as

possible. For the best performance, TI recommends that all the PLL external components be on a single

side of the board without jumpers, switches, or components other than the ones shown in Figure 6-13. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C1, C2, and the EMI Filter).

Figure 6-13. PLL1 and PLL2 External Connection

The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,

see Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).

There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating

frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be

configured not to exceed any of these constraints documented in this section (certain combinations of

external clock inputs, internal dividers, and PLL multiply ratios might not be supported).

110

Peripheral and Electrical Specifications

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