TPS65982ABZBHR datasheet(43/121 Pages) TI1

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Time (200 Ps/div)

-1

-5

D008

I VBUS

VBUS

PP_HV

Time (10 Ps/div)

-5

D007

I VBUS

VBUS

PP_HV

TPS65982

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SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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Figure 27. PP_HV Current Limit Response with a Hard Short

Figure 28. PP_HV Current Limit Response with a Soft Short (7 Ω)

9.3.3.10 External HV Power Delivery

The TPS65982 is capable of controlling an external high-voltage, common-drain back-to-back NMOS FET switch

path to source or sink power up to the maximum limit of the USB PD specification: 20 V at 5 A of current. The

TPS65982 provides external control and sense to external NMOS power switches for currents greater than 3 A.

This path is bi-directional for either sourcing current to VBUS or sinking current from VBUS. The external NMOS

switches are back-to-back to protect the system from large voltage differential across the FETs as well as

blocking reverse current flow. Each NFET has a separate gate control. HV_GATE2 is always connected to the

VBUS side and HV_GATE1 is always connected to the opposite side, referred to as PP_EXT. Two sense pins,

SENSEP and SENSEN, are used to implement reverse current blocking, over-current protection, and current

sensing. The external path may be used in conjunction with the internal path. For example, the internal path may

TPS65982ABZBHR Datasheet(PDF) 43 Page - Texas Instruments