TPS65982ABZBHR datasheet(78/121 Pages) TI1

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Start

Condition

Ack

Nack

Clock Pulse for

Acknowledgement

Data Output

by Transmitter

Data Output

by Receiver

SCL From

Master

Data Line

Change

SDA

SCL

TPS65982

SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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Programming (continued)

(1)

I2C Port 1 ignores the hardware setting of the DEBUG_CTL1 and DEBUG_CTL2 pins and automatically sets these bits to 1 in Bit 4 and

Bit 5 of the address

Figure 71. I2C Bit Transfer

Figure 72. I2C Acknowledgment

9.5.2.2 I2C Clock Stretching

The TPS65982 features clock stretching for the I2C protocol. The TPS65982 slave I2C port may hold the clock

line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The

master communicating with the slave must not finish the transmission of the current bit and must wait until the

clock line actually goes high. When the slave is clock stretching, the clock line will remain low.

The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for

standard 100 kbps I2C) before pulling the clock low again.

Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.

9.5.2.3 I2C Address Setting

The boot code sets the hardware configurable unique I2C address of the TPS65982 before the port is enabled to

respond to I2C transactions. The unique I2C address is determined by a combination of the digital level on the

DEBUG_CTL1/DEBUG_CTL2 pins (two bits) and the analog level set by the analog I2C_ADDR strap pin (three

bits) as shown in Table 9.

Table 9. I2C Default Unique Address

Default I2C Unique Address for Each Port

Port Number

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C Port 1(1)

I2C_ADDR_DECODE[2:0]

R/W

I2C Port 2

DEBUG_CTL2

DEBUG_CTL1

I2C_ADDR_DECODE[2:0]

R/W

TPS65982ABZBHR Datasheet(PDF) 78 Page - Texas Instruments

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