TPS65982ABZBHR datasheet(13/121 Pages) TI1

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TPS65982

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SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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7.6 Power Supervisor Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UV_LDO3V3

Undervoltage threshold for LDO_3V3. Locks out 1.8-V

LDOs

LDO_3V3 rising

2.2

2.325

2.45

UVH_LDO3V3

Undervoltage hysteresis for LDO_3V3

LDO_3V3 falling

150

UV_VBUS_LDO

Undervoltage threshold for VBUS to enable LDO

VBUS rising

3.35

3.75

3.95

UVH_VBUS_LDO

Undervoltage hysteresis for VBUS to enable LDO

VBUS falling

150

UV_PCBL

Undervoltage threshold for PP_CABLE

PP_CABLE rising

2.5

2.625

2.75

UVH_PCBL

Undervoltage hysteresis for PP_PCABLE

PP_CABLE falling

UV_5V0

Undervoltage threshold for PP_5V0

PP_5V0 rising

3.5

3.725

3.95

UVH_5V0

Undervoltage hysteresis for PP_P5V0

PP_5V0 falling

150

OV_VBUS

Overvoltage threshold for VBUS. This value is a 6-bit

programmable threshold

VBUS rising

OVLSB_VBUS

Overvoltage threshold step for VBUS. This value is the

LSB of the programmable threshold

VBUS rising

328

OVH_VBUS

Overvoltage hysteresis for VBUS

VBUS falling, % of OV_VBUS

0.9%

1.3%

1.7%

UV_VBUS

Undervoltage threshold for VBUS. This value is a 6-bit

programmable threshold

VBUS falling

2.5

18.21

UVLSB_VBUS

Undervoltage threshold step for VBUS. This value is the

LSB of the programmable threshold

VBUS falling

249

UVH_VBUS

Undervoltage hysteresis for VBUS

VBUS rising, % of UV_VBUS

0.9%

1.3%

1.7%

UVR_OUT3V3

Configurable undervoltage threshold for VOUT_3V3 rising.

Deasserts RESETZ

Setting 0

2.019

2.125

2.231

Setting 1

2.138

2.25

2.363

Setting 2

2.256

2.375

2.494

Setting 3

2.375

2.5

2.625

Setting 4

2.494

2.625

2.756

Setting 5

2.613

2.75

2.888

Setting 6

2.731

2.875

3.019

Setting 7

2.85

3.15

UVRH_OUT3V3

Undervoltage hysteresis for VOUT_3V3 falling

OUT_3V3 falling

TUVRASSERT

Delay from falling VOUT_3V3 or MRESET assertion to

RESETZ asserting low

μs

TUVRDELAY

Configurable delay from VOUT_3V3 to RESETZ

deassertion

161.3

(1)

Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code

also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity).

(2)

Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active.

(3)

Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and a

selectable clock to the digital core of 3 MHz or 4 MHz.

(4)

Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all

core functionality active, and the digital core is clocked at 12 MHz.

7.7 Power Consumption Characteristics

(1)

Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IVIN_3V3

Sleep(2)

VIN_3V3 = VDDIO = 3.45 V, VBUS = 0,

PPCABLE = 0; 100-kHz oscillator running

µA

Idle (3)

VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE

= 0; 100-kHz oscillator running,

48-MHz oscillator running

1.66

Active(4)

VIN_3V3 = VDDIO = 3.45 V, VBUS = 0,

PPCABLE = 0; 100-kHz Oscillator running,

48-MHz oscillator running

5.64

TPS65982ABZBHR Datasheet(PDF) 13 Page - Texas Instruments

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