TPS65982ABZBHR datasheet(69/121 Pages) TI1

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TPS65982

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SLVSD02D – MARCH 2015 – REVISED JUNE 2019

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9.3.19 Thermal Shutdown

The TPS65982 has both a central thermal shutdown to the chip and a local thermal shutdown for the power path

block. The central thermal shutdown monitors the temperature of the center of the die and disables all functions

except for supervisory circuitry and halts digital core when die temperature goes above a rising temperature of

TSD_MAIN. The temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back

below this value, the device resumes normal operation. The power path block has an local thermal shutdown

circuit to detect an overtemperature condition because of overcurrent and quickly turn off the power switches.

The power path thermal shutdown values are TSD_PWR and TSDH_PWR. The output of the thermal shutdown

circuit is deglitched by TSD_DG before triggering. The thermal shutdown circuits interrupt to the digital core.

9.3.20 Oscillators

The TPS65982 has two independent oscillators for generating internal clock domains. A 48-MHz oscillator

generates clocks for the core during normal operation and clocks for the USB 2.0 endpoint physical layer. An

external resistance is placed on the R_OSC pin to set the oscillator accuracy. A 100-kHz oscillator generates

clocks for various timers and clocking the core during low-power states.

9.4 Device Functional Modes

9.4.1 Boot Code

The TPS65982 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal.

The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core

and the boot code starts executing. Figure 63 provides the TPS65982 boot code sequence.

The TPS65982 boot code is loaded from OTP on POR, and begins initializing TPS65982 settings. This

initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values to

settle, and configuring the device I2C addresses.

The unique I2C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor

configuration on the I2C_ADDR pin.

Once initial device configuration is complete the boot code determines if the TPS65982 is booting under dead

battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65982 is booting under

dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS

power to the system.

TPS65982ABZBHR Datasheet(PDF) 69 Page - Texas Instruments