UJA1069 datasheet(38/64 Pages) PHILIPS

38 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

38 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.13 Test modes

6.13.1 Software development mode

The Software development mode is intended to support software developers in writing

and pretesting application software without having to work around watchdog triggering

and without unwanted jumps to Fail-safe mode.

In Software development mode the following events do not force a system reset:

• Watchdog overﬂow in Normal mode

• Watchdog window miss

• Interrupt time-out

• Elapsed start-up time

However, in case of a watchdog trigger failure the reset source information is still provided

in the System Status register as if there was a real reset event.

The exclusion of watchdog related resets allows simpliﬁed software testing, because

possible problems in the watchdog triggering can be indicated by interrupts instead of

resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode.

This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode

of the SBC.

All transitions to Fail-safe mode are disabled. This allows working with an external

emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more

than tV1(CLT) is the only exception that results in entering Fail-safe mode (to protect the

SBC). Transitions from Start-up mode to Restart mode are still possible.

There are two possibilities to enter Software development mode. One is by setting the

ISDM bit via the Special Mode register; possible only once after a ﬁrst battery connection

while the SBC is in Start-up mode. The second possibility to enter Software development

mode is by applying the correct Vth(TEST) input voltage at pin TEST before the battery is

applied to pin BAT42.

To stay in Software development mode the SDM bit in the Mode register has to be set with

each Mode register access (i.e. watchdog triggering) regardless of how Software

development mode was entered.

The Software development mode can be exited at any time by clearing the SDM bit in the

Mode register. Reentering the Software development mode is only possible by

reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.

UJA1069 Datasheet(PDF) 38 Page - NXP Semiconductors