UJA1069 datasheet(23/64 Pages) PHILIPS

23 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

23 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.10 Interrupt output

Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in

the Interrupt register is set. By reading the Interrupt register all bits are cleared. The

Interrupt register will also be cleared during a system reset (RSTN LOW).

As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN

will be HIGH for at least tINTN after each read-out of the Interrupt register. Without further

interrupts within tINTN pin INTN stays HIGH, otherwise it will revert to LOW again.

To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal

mode some interrupts are only allowed to occur once per watchdog period; see

Section 6.12.7.

If an interrupt is not read out within tRSTN(INT) a system reset is performed.

6.11 Temperature protection

The temperature of the SBC chip is monitored as long as the microcontroller voltage

regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC,

the temperature protection will not switch off any part of the SBC or activate a deﬁned

system stop of its own accord. If the temperature is too high it generates an interrupt to

the microcontroller, if enabled, and the corresponding status bit will be set. The

microcontroller can then decide whether to switch off parts of the SBC to decrease the

chip temperature.

Fig 13. Pin WAKE, cyclic sampling via V3

sample

active

VWAKE

flip flop

VINTN

ton(CS)

tw(CS)

tsu(CS)

approximately 70 %

signal already HIGH

due to biasing (history)

signal remains LOW

due to biasing (history)

button pushed

button released

001aac307

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