UJA1069 datasheet(47/64 Pages) PHILIPS

47 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

47 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125

°C ambient

temperature on wafer level (pretesting). Cased products are 100 % tested at 25

°C ambient temperature (ﬁnal testing). Both pretesting

and ﬁnal testing use correlated test conditions to cover the speciﬁed temperature and power supply voltage range.

[2]

VV1(nom) is 3 V, 3.3 V or 5 V, depending on the SBC version.

[3]

Not tested in production.

IRTLIN(pu)

RTLIN pull-up

current

Active mode;

VRTLIN =VLIN =0V;

t>tLIN(dom)(det)

−150

−60

−35

µA

Off-line mode;

VRTLIN =VLIN =0V;

t<tLIN(dom)(det)

−150

−60

−35

µA

ILL

LOW-level leakage

current

Off-line mode;

VRTLIN =VLIN =0V;

t>tLIN(dom)(det)

−10

+10

µA

TEST input; pin TEST

Vth(TEST)

input threshold

voltage

for entering Software

development mode;

Tj =25 °C

158V

for entering Forced normal

mode; Tj =25 °C

13.5

R(pd)TEST

pull-down resistor

between pin TEST and GND

248k

Ω

Temperature detection

Tj(warn)

high junction

temperature warning

level

160

175

190

°C

Table 25.

Static characteristics …continued

Tvj = −40 °C to +150 °C, VBAT42 = 5.5 Vto52 V;VBAT14 = 5.5 Vto27 V;VBAT42 ≥ VBAT14 − 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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