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UJA1069 Datasheet(PDF) 16 Page - NXP Semiconductors |
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UJA1069 Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 64 page  UJA1069_2 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 — 5 March 2007 16 of 64 NXP Semiconductors UJA1069 LIN fail-safe system basis chip Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(CLT), the SBC immediately enters Fail-safe mode since this indicates an application failure. Fig 7. Reset pin behavior Fig 8. Reset timing diagram VRSTN power-up power- down under- voltage missing watchdog access under- voltage spike V1 time time Vrel(UV)(V1) Vdet(UV)(V1) coa054 tRSTNL tRSTNL tRSTNL 001aad181 RSTN externally forced LOW RSTN externally forced LOW time time VRSTN VRSTN tRSTNL tWD(init) tRSTNL tWD(init) |
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