UJA1069 datasheet(18/64 Pages) PHILIPS

18 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

18 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.6.4 Switched battery output V3

V3 is a high-side switched BAT42-related output which is used to drive external loads

such as wake-up switches or relays. The features of V3 are as follows:

• Three application controlled modes of operation; ON, OFF or Cyclic mode.

• Two different cyclic modes allow the supply of external wake-up switches; these

switches are powered intermittently, thus reducing the system’s power consumption in

case a switch is continuously active; the wake-up input of the SBC is synchronized

with the V3 cycle time.

• The switch is protected against current overloads. If V3 is overloaded, pin V3 is

automatically disabled. The corresponding Diagnosis register bit is reset and an

interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the

corresponding reset source code becomes available in the RSS bits of the System

Status register. This signals that the wake-up source via V3 supplied wake-up

switches has been lost.

6.7 LIN transceiver

The integrated LIN transceiver of the UJA1069 is a LIN 2.0 compliant transceiver. The

transceiver has the following features:

• SAE J2602 compliant and compatible with LIN revision 1.3

• Fail-safe LIN termination to BAT42 via dedicated RTLIN pin

• Enhanced error handling and reporting of bus and TXD failures; these failures are

separately identiﬁed in the System Diagnosis register

6.7.1 Mode control

The controller of the LIN transceiver provides two modes of operation: Active mode and

Off-line mode; see Figure 9. In Off-line mode the transmitter and receiver do not consume

current, but wake-up events will be recognized by the separate wake-up receiver.

UJA1069 Datasheet(PDF) 18 Page - NXP Semiconductors