UJA1069 datasheet(15/64 Pages) PHILIPS

15 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

15 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.5 System reset

The reset function of the UJA1069 offers two signals to deal with reset events:

• RSTN; the global ECU system reset

• EN; a fail-safe global enable signal

6.5.1 RSTN pin

The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with

selectable pulse length upon the following events; see Figure 4:

• Power-on (ﬁrst battery connection) or VBAT42 below power-on reset threshold voltage

• Low V1 supply

• V1 current above threshold during Standby mode while watchdog OFF behavior is

selected

• V3 is down due to short-circuit condition during Sleep mode

• RSTN externally forced LOW, falling edge event

• Successful preparation for Flash mode completed

• Successful exit from Flash mode

• Wake-up from Standby mode via pins LIN or WAKE if programmed accordingly, or any

wake-up event from Sleep mode

• Wake-up event from Fail-safe mode

• Watchdog trigger failures (too early, overﬂow, wrong code)

• Illegal mode code via SPI applied

• Interrupt not served within tRSTN(INT)

All of these reset events have a dedicated reset source in the System Status register to

allow distinction between the different events.

The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware

is properly reset. After the ﬁrst battery connection, a short power-on reset of 1 ms is

provided after voltage V1 is present. Once started, the microcontroller can set the Reset

Length Control (RLC) bit within the System Conﬁguration Register; this allows the reset

pulse to be adjusted for future reset events. With this bit set, all reset events are

lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)

in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an

erroneously shortened reset pulse will restart any microcontroller, at least within the

second trial by using the long reset pulse.

The behavior of pin RSTN is illustrated in Figure 7. The duration of tRSTNL depends on the

setting of the RLC bit (deﬁnes the reset length). Once an external reset event is detected

the system controller enters the Start-up mode. The watchdog now starts to monitor pin

RSTN as illustrated in Figure 8. If the RSTN pin is not released in time then Fail-safe

mode is entered as shown in Figure 4.

UJA1069 Datasheet(PDF) 15 Page - NXP Semiconductors

UJA1069 Datasheet(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL