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PSD4235G2 Datasheet(PDF) 73 Page - STMicroelectronics |
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PSD4235G2 Datasheet(HTML) 73 Page - STMicroelectronics |
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73 / 89 page ![]() 73/89 PSD4235G2 Table 63. CPLD Macrocell Asynchronous Clock Mode Timing Symbol Parameter Conditions -70 -90 PT Aloc Turbo Off Slew Rate Unit MinMax MinMax fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 38.4 26.32 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 62.5 35.71 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 47.6 37.03 MHz tSA Input Setup Time 6 8 + 2 + 12 ns tHA Input Hold Time 7 12 ns tCHA Clock Input High Time 9 12 + 12 ns tCLA Clock Input Low Time 12 15 + 12 ns tCOA Clock to Output Delay 21 30 + 12 – 2 ns tARDA CPLD Array Delay Any Macrocell 11 16 + 2 ns tMINA Minimum Clock Period 1/fCNTA 16 28 ns |
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