PSD4235G2 datasheet(23/89 Pages) STMICROELECTRONICS

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PSD4235G2

Instructions

An instruction consists of a sequence of specific

operations. Each received byte is sequentially de-

coded by the PSD and not executed as a standard

Write operation. The instruction is executed when

the correct number of bytes are properly received

and the time between two consecutive bytes is

shorter than the time-out period. Some instruc-

tions are structured to include Read operations af-

ter the initial Write operations.

The instruction must be followed exactly. Any in-

valid combination of instruction bytes or time-out

between two consecutive bytes while addressing

Flash memory resets the device logic into Read

mode (Flash memory is read like a ROM device).

The PSD supports the instructions summarized in

Table 29:

Erase memory by chip or sector

Suspend or resume sector erase

Program a Word

Reset to Read mode

Read primary Flash Identifier value

Read Sector Protection Status

Bypass

These instructions are detailed in Table 29. For ef-

ficient decoding of the instructions, the first two

bytes of an instruction are the coded cycles and

are followed by an instruction byte or confirmation

byte. The coded cycles consist of writing the data

AAh to address XAAAh during the first cycle and

data 55h to address X554h during the second cy-

cle (unless the Bypass instruction feature is used,

as described later). Address signals A15-A12 are

Don’t Care during the instruction Write cycles.

However, the appropriate Sector Select signal

(FS0-FS7, or CSBOOT0-CSBOOT3) must be se-

lected.

The primary and secondary Flash memories have

the same instruction set (except for Read Primary

Flash Identifier). The Sector Select signals deter-

mine which Flash memory is to receive and exe-

cute the instruction. The primary Flash memory is

selected if any one of its Sector Select signals

(FS0-FS7) is High, and the secondary Flash mem-

ory is selected if any one of its Sector Select sig-

nals (CSBOOT0-CSBOOT3) is High.

Power-up Condition. The PSD internal logic is

reset upon Power-up to the Read mode. Sector

Select

(FS0-FS7

and

CSBOOT0-CSBOOT3)

must be held Low, and Write Strobe (WR/WRL,

CNTL0) High, during Power-up for maximum se-

curity of the data contents and to remove the pos-

sibility of data being written on the first edge of

Write Strobe (WR/WRL, CNTL0). Any Write cycle

initiation is locked when VCC is below VLKO.

Reading Flash Memory

Under typical conditions, the MCU may read the

primary Flash memory, or secondary Flash mem-

ory, using Read operations just as it would a ROM

or RAM device. Alternately, the MCU may use

Read operations to obtain status information

about a Program or Erase cycle that is currently in

progress. Lastly, the MCU may use instructions to

read special data from these memory blocks. The

following sections describe these Read functions.

Read Memory Contents. Primary Flash memory

and secondary Flash memory are placed in the

Read mode after Power-up, chip reset, or a Reset

Flash instruction (see Table 29). The MCU can

read the memory contents of the primary Flash

memory, or the secondary Flash memory by using

Read operations any time the Read operation is

not part of an instruction.

Read Primary Flash Identifier. The

primary

Flash memory identifier is read with an instruction

composed of 4 operations: 3 specific Write opera-

tions and a Read operation (see Table 29). The

identifier for the primary Flash memory is E8h. The

secondary Flash memory does not support this in-

struction.

Read Memory Sector Protection Status. The

Flash memory Sector Protection Status is read

with an instruction composed of four operations:

three specific Write operations and a Read opera-

tion (see Table 29). The Read operation produces

01h if the Flash memory sector is protected, or 00h

if the sector is not protected.

The sector protection status for all NVM blocks

(primary Flash memory, or secondary Flash mem-

ory) can be read by the MCU accessing the Flash

Protection and Flash Boot Protection registers in

PSD I/O space. See the section entitled “Flash

Memory Sector Protect”, on page 27, for register

definitions.

Reading the Erase/Program Status Bits. The

PSD provides several status bits to be used by the

MCU to confirm the completion of an Erase or Pro-

gram cycle of Flash memory. These status bits

minimize the time that the MCU spends perform-

ing these tasks and are defined in Table 30. The

status byte resides in an even location, and can be

read as many times as needed. Also note that

DQ15-DQ8 is an even byte for Motorola MCUs

with a 16-bit data bus.

For Flash memory, the MCU can perform a Read

operation to obtain these status bits while an

Erase or Program instruction is being executed by

the embedded algorithm. See the section entitled

“Programming Flash Memory”, on page 25, for de-

tails.

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