AT89C51ID2-RDTIM datasheet(118/159 Pages) ATMEL

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118

AT89C51ID2

4289A–8051–09/03

Flash Registers and

Memory Map

The AT89C51ID2 Flash memory uses several registers for his management:

•

Hardware registers can only be accessed through the parallel programming modes

which are handled by the parallel programmer.

•

Software registers are in a special page of the Flash memory which can be

accessed through the API or with the parallel programming modes. This page,

called "Extra Flash Memory", is not in the internal Flash program memory

addressing space.

Hardware Register

The only hardware register of the AT89C51ID2 is called Hardware Security Byte (HSB).

Table 87. Hardware Security Byte (HSB)

Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

•

When this bit is set the boot address is 0000h.

•

When this bit is reset the boot address is F800h. By default, this bit is cleared and

the ISP is enabled.

Flash Memory Lock Bits

The three lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown in Table 88.

7654

3210

BLJB

OSC

XRAM

LB2

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

7X2

X2 Mode

Programmed to force X2 mode (6 clocks per instruction)

Unprogrammed to force X1 mode, Standard Mode. (Default)

6BLJB

Boot Loader Jump Bit

Unprogrammed this bit to start the user’s application on next reset at address

0000h.

Programmed this bit to start the boot loader at address F800h (Default).

5OSC

Oscillator Bit

Programmed to allow oscillator B at startup

Unprogrammed this bit to allow oscillator A at startup ( Default).

Reserved

3XRAM

XRAM config bit (only programmable by programmer tools)

Programmed to inhibit XRAM

Unprogrammed, this bit to valid XRAM (Default)

2-0

LB2-0

User Memory Lock Bits (only programmable by programmer tools)

See Table 88

AT89C51ID2-RDTIM Datasheet(PDF) 118 Page - ATMEL Corporation

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