ADSP-BF504 datasheet(36/80 Pages) AD

36 / 80 page

Rev. PrC

Page 36 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

RSI Controller Timing

Table 26 and Figure 16 describe RSI Controller Timing.

Table 27 and Figure 17 describe RSI controller (high speed)

timing.

Table 26. RSI Controller Timing

Parameter

Min

Max

Unit

Timing Requirements

tISU

Input Setup Time

5.6

tIH

Input Hold Time

Switching Characteristics

fPP

Clock Frequency Data Transfer Mode

MHz

fOD

Clock Frequency Identification Mode

100

400

kHz

tWL

Clock Low Time

tWH

Clock High Time

tTLH

Clock Rise Time

tTHL

Clock Fall Time

tODLY

Output Delay Time During Data Transfer Mode

tODLY

Output Delay Time During Identification Mode

1 t

PP = 1/fPP

2 Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

Figure 16. RSI Controller Timing

SD_CLK

INPUT

OUTPUT

tISU

NOTES:

1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

tTHL

tTLH

tWL

tWH

tPP

tIH

tODLY

VOH (MIN)

VOL (MAX)

ADSP-BF504 Datasheet(PDF) 36 Page - Analog Devices

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