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ADSP-BF504 Datasheet(PDF) 38 Page - Analog Devices

Part # ADSP-BF504
Description  Blackfin Embedded Processor
PDF  80 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF504 Datasheet(HTML) 38 Page - Analog Devices

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Rev. PrC
|
Page 38 of 80
|
January 2010
ADSP-BF504/F,ADSP-BF506F
Preliminary Technical Data
Serial Ports
Table 28 through Table 31 on Page 40 and Figure 18 on Page 39
through Figure 20 on Page 40 describe serial port operations.
Table 28. Serial Ports—External Clock
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5/3.3 V
Min
Max
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
3.0
3.0
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
3.0
3.0
ns
tSDRE
Receive Data Setup Before RSCLKx
1,2
3.0
3.0
ns
tHDRE
Receive Data Hold After RSCLKx1,2
3.6
3.6
ns
tSCLKEW
TSCLKx/RSCLKx Width
5.4
5.4
ns
tSCLKE
TSCLKx/RSCLKx Period
18.0
18.0
ns
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
12.5
12.0
ns
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
0.0
0.0
ns
tDDTE
Transmit Data Delay After TSCLKx3
12.5
12.0
ns
tHDTE
Transmit Data Hold After TSCLKx
3
0.0
0.0
ns
1 Referenced to sample edge.
2 When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 39 (ACM Timing).
3 Referenced to drive edge.
Table 29. Serial Ports—Internal Clock
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5/3.3 V
Min
Max
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
12.4
11.3
ns
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
–1.5
–1.5
ns
tSDRI
Receive Data Setup Before RSCLKx1,2
12.4
11.3
ns
tHDRI
Receive Data Hold After RSCLKx1,2
–1.5
–1.5
ns
Switching Characteristics
tSCLKIW
TSCLKx/RSCLKx Width
5.4
5.4
ns
tSCLKI
TSCLKx/RSCLKx Period
18.0
18.0
ns
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
3.0
3.0
ns
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
–4.0
–4.0
ns
tDDTI
Transmit Data Delay After TSCLKx
3
3.0
3.0
ns
tHDTI
Transmit Data Hold After TSCLKx
3
–1.8
–1.8
ns
1 Referenced to sample edge.
2 When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 39 (ACM Timing).
3 Referenced to drive edge.



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