ADSP-BF504 datasheet(57/80 Pages) AD

57 / 80 page

Preliminary Technical Data

Rev. PrC

Page 57 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

ADC — TIMING SPECIFICATIONS

ADC — ABSOLUTE MAXIMUM RATINGS

Stresses above those listed in Table 49 may cause permanent

damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above

those indicated in the operational section of this specification is

not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Table 48. Serial Data Interface1

1 See also Figure 93 on Page 71 and Figure 94 on Page 71.

Parameter

Limit at TMIN, TMAX

Unit

Description/Conditions

fADSCLK

2 Minimum ADSCLK for specified performance; with slower ADSCLK frequencies, performance specifications apply typically.

4/32

MHz min/max

tCONVERT

14 × tADSCLK

ns max

tADSCLK = 1/fADSCLK

437.5

ns max

fADSCLK = 32 MHz, fSAMPLE = 2 MSPS; AVDD, DVDD = 5 V

583.3

ns max

fADSCLK = 24 MHz, fSAMPLE = 1.5 MSPS; AVDD, DVDD = 3 V

tQUIET

ns min

Minimum time between end of serial read and next falling edge of CS

20/30

ns min

CS to ADSCLK setup time; VDRIVE = 5 V/3 V

ns max

Delay from CS until DOUTA and DOUTB are three-state disabled

3 The time required for the output to cross 0.4 V or 2.4 V.

27/36

ns max

Data access time after ADSCLK falling edge, VDRIVE = 5 V/3 V

0.45 tADSCLK

ns min

ADSCLK low pulse width

0.45 tADSCLK

ns min

ADSCLK high pulse width

5/10

ns min

ADSCLK to data valid hold time, VDRIVE = 5 V/3 V

ns max

CS rising edge to DOUTA, DOUTB, high impedance

ns min

CS rising edge to falling edge pulse width

t10

5/35

ns min/max

ADSCLK falling edge to DOUTA, DOUTB, high impedance

Table 49. Absolute Maximum Ratings

Parameter

Rating

AVDD, DVDD to AGND

–0.3 V to +7 V

DVDD to DGND

–0.3 V to +7 V

VDRIVE to DGND

–0.3 V to DVDD

VDRIVE to AGND

–0.3 V to AVDD

AVDD to DVDD

–0.3 V to +0.3 V

AGND to DGND

–0.3 V to +0.3 V

Analog Input Voltage to AGND

–0.3 V to AVDD + 0.3 V

Digital Input Voltage to DGND

–0.3 V to +7 V

Digital Output Voltage to GND

–0.3 V to VDRIVE + 0.3 V

VREF to AGND

–0.3 V to AVDD + 0.3 V

Input Current to Any ADC Pin

Except Supplies

1 Transient currents of up to 100 mA will not cause latch up.

±10 mA

Storage Temperature Range

–65°C to +150°C

Junction Temperature Under Bias

+110°C

ADSP-BF504 Datasheet(PDF) 57 Page - Analog Devices

ADSP-BF504 Datasheet(HTML) 57 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL