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ADSP-BF504 Datasheet(PDF) 25 Page - Analog Devices |
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ADSP-BF504 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 80 page ![]() Preliminary Technical Data Rev. PrC | Page 25 of 80 | January 2010 ADSP-BF504/F,ADSP-BF506F PROCESSOR — SPECIFICATIONS Specifications are subject to change without notice. PROCESSOR — OPERATING CONDITIONS Table 13 shows settings for TWI_DT in the NONGPIO_DRIVE register. Set this register prior to using the TWI port. Parameter Conditions Min Nominal Max Unit VDDINT 1 1 The expected nominal value is 1.4 V ±5%, and initial customer designs should design with a programmable regulator that can be adjusted from 0.95 V to 1.5 V in 50 mV steps. Internal Supply Voltage TBD TBD TBD V VDDEXT 2 2 Must remain powered (even if the associated function is not used). External Supply Voltage ADSP-BF504 1.7 1.8 /2.5 / 3.3 3.6 V VDDEXT 2 External Supply Voltage ADSP-BF504F, ADSP-BF506F 2.7 3.3 3.6 V VDDFLASH 2,3 3 For ADSP-BF504, VDDFLASH pins should be connected to GND. Flash Memory Supply Voltage 1.7 1.8 2.0 V VIH High Level Input Voltage4, 5 4 Bidirectional pins (PF15–0, PG15–0, PH2–0) and input pins (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF50x processors are 3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 5 Parameter value applies to all input and bidirectional pins, except SDA and SCL. VDDEXT = 1.90 V 1.1 3.6 V VIH High Level Input Voltage4, 5 VDDEXT = 2.75 V 1.7 3.6 V VIH High Level Input Voltage 4, 5 VDDEXT = 3.6 V 2.0 3.6 V VIHTWI High Level Input Voltage 6 6 Parameter applies to SDA and SCL. VDDEXT = 1.90 V/2.75 V/3.6 V 0.7 × VBUSTWI 7, 8 VBUSTWI 7, 8 7 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 13. V VIL Low Level Input Voltage 4, 5 VDDEXT = 1.7 V –0.3 0.6 V VIL Low Level Input Voltage4, 5 VDDEXT = 2.25 V –0.3 0.7 V VIL Low Level Input Voltage4, 5 VDDEXT = 3.0 V –0.3 0.8 V VILTWI Low Level Input Voltage6 VDDEXT = minimum –0.3 0.3 × VBUSTWI 8 8 SDA and SCL are pulled up to VBUSTWI. See Table 13. V TJ Junction Temperature 88-Lead LFCSP @ T AMBIENT = –40°C to + 85°C –40 +105 °C TJ Junction Temperature 120-Lead LQFP @ T AMBIENT = –40°C to +85°C –40 +105 °C Table 13. TWI_DT Field Selections and VDDEXT/VBUSTWI TWI_DT VDDEXT Nominal VBUSTWI Minimum VBUSTWI Nominal VBUSTWI Maximum Unit 000 (default) 3.3 2.97 3.3 3.63 V 001 1.8 1.7 1.8 1.98 V 010 2.5 2.97 3.3 3.63 V 011 1.8 2.97 3.3 3.63 V 100 3.3 4.5 5 5.5 V 101 1.8 2.25 2.5 2.75 V 110 2.5 2.25 2.5 2.75 V 111 (reserved) – – – – – |
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