ADSP-BF504 datasheet(68/80 Pages) AD

68 / 80 page

Rev. PrC

Page 68 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

down for a relatively long duration between these bursts of sev-

eral conversions. When the ADC is in partial power-down, all

analog circuitry is powered down except for the on-chip refer-

ence and reference buffer.

To enter partial power-down mode, the conversion process

must be interrupted by bringing CS high anywhere after the sec-

ond falling edge of ADSCLK and before the 10th falling edge of

ADSCLK, as shown in Figure 87 (Entering Partial Power-Down

Mode). Once CS is brought high in this window of ADSCLKs,

the part enters partial power-down, the conversion that was ini-

tiated by the falling edge of CS is terminated, and DOUTA and

DOUTB go back into three-state. If CS is brought high before the

second ADSCLK falling edge, the part remains in normal mode

and does not power down. This avoids accidental power-down

due to glitches on the CS line.

To exit this mode of operation and power up the ADC again, a

dummy conversion is performed. On the falling edge of CS, the

device begins to power up and continues to power up as long as

CS is held low until after the falling edge of the 10th ADSCLK.

The device is fully powered up after approximately 1 μs has

elapsed, and valid data results from the next conversion, as

shown in Figure 88 (Exiting Partial Power-Down Mode). If CS

is brought high before the second falling edge of ADSCLK, the

ADC again goes into partial power-down. This avoids acciden-

tal power-up due to glitches on the CS line. Although the device

may begin to power up on the falling edge of CS, it powers down

again on the rising edge of CS. If the ADC is already in partial

power-down mode and CS is brought high between the second

and 10th falling edges of ADSCLK, the device enters full power-

down mode.

Full Power-Down Mode

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes substan-

tially longer than that from partial power-down. This mode is

more suited to applications where a series of conversions per-

formed at a relatively high throughput rate are followed by a

long period of inactivity and thus power-down. When the ADC

is in full power-down, all analog circuitry is powered down. Full

power-down is entered in a similar way as partial power-down,

except the timing sequence shown in Figure 87 (Entering Partial

Power-Down Mode) must be executed twice. The conversion

process must be interrupted in a similar fashion by bringing CS

high anywhere after the second falling edge of ADSCLK and

before the 10th falling edge of ADSCLK. The device enters par-

tial power-down at this point. To reach full power-down, the

next conversion cycle must be interrupted in the same way, as

shown in Figure 89 (Entering Full Power-Down Mode). Once

CS is brought high in this window of ADSCLKs, the part com-

pletely powers down.

Note that it is not necessary to complete the 14 ADSCLKs once

CS is brought high to enter a power-down mode.

To exit full power-down and power up the ADC, a dummy con-

version is performed, as when powering up from partial power-

down. On the falling edge of CS, the device begins to power up

and continues to power up, as long as CS is held low until after

the falling edge of the 10th ADSCLK. The required power-up

time must elapse before a conversion can be initiated, as shown

in Figure 90 (Exiting Full Power-Down Mode). See the Power-

Up Times section for the power-up times associated with the

ADC.

Figure 87. Entering Partial Power-Down Mode

ADSCLK

THREE-STATE

DOUTA

DOUTB

114

Figure 88. Exiting Partial Power-Down Mode

ADSCLK

DOUTA

DOUTB

INVALID DATA

VALID DATA

110

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY

POWERED UP; SEE

POWER-UP TIMES

SECTION.

tPOWER-UP1

ADSP-BF504 Datasheet(PDF) 68 Page - Analog Devices

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