SPEAR1340 datasheet(106/200 Pages) STMICROELECTRONICS

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Pin description

SPEAr1340

106/200

Doc ID 023063 Rev 4

3.5.5

Connectivity

Table 15.

Connectivity - MAC PHY interface signals description

Signal name

Description

Type

Ball

MAC_GTXCLK125

Auxiliary source of clock

T28

MAC_GTXCLK

Transmission clock

This is the transmission clock provided by the external

PHY/oscillator/internal PLL for the RGMII,GMII, RMII. All the RGMII,GMII,

RMII transmission signals generated by the MAC are synchronous to this

clock.

RMII: this clock is used also as receive clock, so all the receive signals are

synchronous to this clock.

OR28

MAC_TXCLK

Transmission clock

This is the transmission clock (25/2.5 MHz in 100M/10Mbps) provided by

the external PHY for the MII. All the MII transmission signals generated by

the MAC are synchronous to this clock.

IU28

MAC_TXD0

PHY transmit data

This is a bundle of eight transmit data signals driven by the MAC. It has

multiple functions depending on which PHY interface is selected, as given

below. Unused bits in the RGMII,RMII,MII interface configurations are tied

to low.

– GMII: All 8 bits provide the GMII transmit data byte. The validity of the

data is qualified with MAC_TXEN and MAC_TXER.

Note: Using 10/100 Mbps-only operation, MAC_TXD bus is only 4 bits

wide (MAC_TXD[3:0]).

– MII: Bits [3:0] provide the MII transmit data nibble. The validity of the

data is qualified with MAC_TXEN and MAC_TXER.

– RGMII: Bits [3:0] provide the RGMII transmit data. The data bus

changes with both rising and falling edges of the transmit clock. The

validity of the data is qualified with MAC_TXEN.

– RMII: Bits [1:0] provide the RMII transmit data. The validity of the data is

qualified with MAC_TXEN.

U27

MAC_TXD1

T26

MAC_TXD2

T27

MAC_TXD3

T25

MAC_TXD4

R25

MAC_TXD5

R26

MAC_TXD6

P26

MAC_TXD7

P27

MAC_TXEN

PHY transmit data enable

This signal is driven by the MAC and has multiple functions depending on

which PHY interface is selected, as given below.

– GMII/MII/RMII: When high, indicates that valid data is being transmitted

on the MAC_TXD bus.

– RGMII: This signal is the control signal for the transmit data, and is

driven on both edges of the clock.

L24

MAC_TXER

PHY transmit error

This signal is driven by the MAC and has multiple functions depending on

which PHY interface is selected, as given below.

– GMII/MII: When high, indicates a transmit error or carrier extension (in

GMII) on the MAC_TXD bus.

– RMII, RGMII: Not used. Tied low in some configurations; driven low in

others.

L25

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