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SPEAR1340 Datasheet(PDF) 130 Page - STMicroelectronics |
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SPEAR1340 Datasheet(HTML) 130 Page - STMicroelectronics |
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130 / 200 page  Pin description SPEAr1340 130/200 Doc ID 023063 Rev 4 3.6 Strapping options The following two tables show the strapping options available (STRAP[6:0]) on SPEAr1340. STRAP[6:0] pins are sampled at reset release and they are reusable after the internal latching for different purposes. When used as output pins, these pins require no special conditions, but when used as input pins, the application must keep them in a non-driving (tri- state) mode for at least 2 µs after MRESETn is released. STRAP[6:0] pins are sampled by internal hardware logic during the power-on reset sequence and latched on the BOOTSTRAP_CFG register in the MISC. Table 37. Strapping options Signal name Description Type Ball STRAP0 The BootROM firmware selects the booting device after reset release by reading the status of the STRAP[3:0] pins. S AE19 STRAP1 SAH20 STRAP2 SAD19 STRAP3 SAD20 STRAP4 Used to select the usage of NAND Flash 8-bit interface working as 3V3 or 1V8, along with CE0n: STRAP4= 1 --> 3V3 STRAP4= 0 --> 1V8 S AE20 STRAP5 Used to select the usage of NAND Flash extension to 16-bit interface and/or second chip select CE1n working as 3V3 or 1V8: STRAP5= 1 --> 3V3 STRAP5= 0 --> 1V8 SAF20 STRAP6 Used to select the GMII/RGMII interface working at 3V3 or 2V5: STRAP6= 1 --> 2V5 STRAP6= 0 --> 3V3 SAG20 Table 38. Hardware boot selection (STRAP[0..3]) Primary source Backup source(1) STRAP3 STRAP2 STRAP1 STRAP0 Bypass na 0 0 0 0 Serial NOR Flash(2) USB OTG (Device) 00 01 NAND Flash(3) USB OTG (Device) 00 10 Parallel NOR Flash (8-bit)(3) USB OTG (Device) 00 11 Parallel NOR Flash (16-bit)(3) USB OTG (Device) 01 00 UART na 01 01 rfu(4) na 01 10 rfu na 0 1 1 1 USB OTG (Device) na 1 0 0 0 Serial NOR Flash(2) UART 10 01 NAND Flash(3) UART 10 10 |
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