SPEAR1340 datasheet(134/200 Pages) STMICROELECTRONICS

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Electrical characteristics

SPEAr1340

134/200

Doc ID 023063 Rev 4

4.3

Clocking parameters

4.3.1

Master clock (MCLK)

External clock generated from a crystal oscillator

Figure 7.

MCLK crystal connection

CL1 and CL2 are the load capacitors.

The value of the capacitors depends on the type of the selected crystal. To calculate the

value of the load capacitance, use the formula given below.

For this example, Aker C2E-24.000-12-3030-X 24 MHz oscillator has been used.

Formula

--------------------------

Where CL1 and CL2 are the load capacitors and CS is the circuit stray capacitance.

In our application:

CL1

= CL2 = Cext

Table 42.

MCLK oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fosc_in

Oscillator frequency

24(1)

A frequency of 24 MHz is mandatory to obtain the required frequencies for all clocks generated by the PLL

of the USB PHY.

33 (2)

At Max freq = 33 MHz the ESR value has to be less than 20

Ω.

MHz

ESR

Equivalent series

resisistance

Oscillator

transconductance

Startup

19.8

28.5

mA/V

tSU

Startup time

Stabilized power on

MCLK_AVDD3V3

2 (3)

Startup time simulated with a 30 MHz crystal.

VDD3v3

24 MHz

CL1

CL2

(1)

MCLK_XI

MCLK_XO

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