SPEAR1340 datasheet(162/200 Pages) STMICROELECTRONICS

162 / 200 page

Timing characteristics

SPEAr1340

162/200

Doc ID 023063 Rev 4

5.6.3

SRAM configuration timing characteristics

Figure 24.

SRAM configuration timing waveform

TAD, TBL, TD, TW, TR and TSTROBE are fixed values: they depend only on the internal timings

of SPEAr.

TADDR_ST and TDATA_ST are programmable timings defined by FSMC registers. They can be

calculated as:

TADDR_ST = (Addr_ST + 1) * THCLK (min value for Addr_ST is 0)

TDATA_ST = Data_ST * THCLK (min value for Data_ST is 0 for Read and 1 for Write)

Since the data strobe always happens 1 HCLK cycle before the rising edge of the chip

select, TSTROBE can be calculated as:

TSTROBE = THCLK - TW

THCLK = 6 ns (period of the AHB clock, the FSMC input clock)

TMEM is the output delay of the Static RAM.

The FSCM_REn signal can toggle either after the de-assertion of the chip select

(Extended_Mode = 0) or after the Addr_ST phase (Extended_Mode = 1).

In the 1st case the programmable timings for Read and Write are unique while in the 2nd

case they can be different from each other.

When writing a data, since the SRAM strobes it on the rising edge of FSMC_WEn, the user

should choose the correct values of Data_ST in order to satisfy the setup constraint:

THCLK + TW + TDATA_ST - TD ≥ TSETUP (SRAM)

FSMC_CExn

FSMC_AD [25:0]

FSMC_WEn

FSMC_IO (out)

DATAOUT

FSMC_REn

FSMC_IO (in)

DATAIN

ADDRESS

FSMC_BL0n_AV

FSMC_BL1n

DATAIN

tADDR_ST + tW

tDATA_ST

tADDR_ST - tHCLK+ tD

tMEM

tBL

tAD

tSTROBE

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