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SPEAR1340 Datasheet(PDF) 164 Page - STMicroelectronics

Part # SPEAR1340
Description  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1340 Datasheet(HTML) 164 Page - STMicroelectronics

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Timing characteristics
SPEAr1340
164/200
Doc ID 023063 Rev 4
5.7
GMAC timing characteristics
This section describes the AC timing characteristics for the Giga/Fast Ethernet port. The
GMAC is designed to support 10, 100 and 1000 Mbps Ethernet/IEEE 802.3 networks. It
supports GMII, RMII and MII interfaces.
Note:
For the pin list of the supported interfaces, see Table 5: MAC Ethernet port multiplexing
scheme and Table 15: Connectivity - MAC PHY interface signals description.
5.7.1
GMII transmit timing characteristics
The timing characterization is performed assuming an output load capacitance of 10 pF on
the output pads and using PLL2 as internal clock source or MAC_GTXCLK125 as external
clock source for GMII TX interface timings extraction.
These timings are valid for 10, 100 and 1000 Mbps operation.
Figure 25.
GMII TX timing waveform
MAC_GTXCLK
(output)
MAC_TXD0 - MAC_TXD7,
MAC_TXEN, MAC_TXER
TCLKhigh
TCLKlow
TD
Table 73.
GMII TX timing characteristics
Parameter
Description
Conditions(1)
Min
Max
Unit
TCLK
MAC_GTXCLK clock period
8
ns
TCLKhigh
MAC_GTXCLK pulse high
Clock source=
MAC_GTXCLK125@125 MHz
(50% ideal duty cycle)
1.5
ns
TCLKlow
MAC_GTXCLK pulse low
1.0
ns
TCLKhigh
MAC_GTXCLK pulse high
Clock source=
MAC_GTXCLK125@250 MHz
internally divided by 2
2.1
ns
TCLKlow
MAC_GTXCLK pulse low
1.4
ns
TCLKhigh
MAC_GTXCLK pulse high
Clock source= PLL2
2.2
ns
TCLKlow
MAC_GTXCLK pulse low
1.2
ns
TD
MAC_GTXCLK to GMII output
data
0.4
5.6
ns
1.
Characterizations based on external clock sources are performed assuming an ideal 50% duty cycle clock.



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