SPEAR1340 datasheet(184/200 Pages) STMICROELECTRONICS

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Timing characteristics

SPEAr1340

184/200

Doc ID 023063 Rev 4

Figure 46.

SPI master mode external timing waveform (SPH = 1, SPO = 1)

5.15.2

SPI slave mode timings

Table 98.

SPI master mode timing characteristics (clock phase bit SPH = 1, SPO=0)

Symbol

Parameters

Min

Max

Unit

TSU

Setup time, MISO (input) valid before

SSP_SCK (output) falling edge

17.8

Hold time, MISO (input) valid after SSP_SCK

(output) falling edge

TD1

Delay time, SSP_SS#n (output) falling edge to

first SSP_SCK (output) falling edge

TSSP_SCK-8

TSSP_SCK-2

TD2

Delay time, SSP_SCK (output) rising edge to

MOSI (output) transition

-3.8

12.5

TD3

Delay time, SSP_SCK (output) falling edge to

SSP_SS#n (output) rising edge

TSSP_SCK + 2 TSSP_SCK +8

Table 99.

SPI master mode timing characteristics (clock phase bit SPH = 1, SPO=1)

Symbol

Parameters

Min

Max

Unit

TSU

Setup time, MISO (input) valid before

SSP_SCK (output) rising edge

Hold time, MISO (input) valid after SSP_SCK

(output) rising edge

TD1

Delay time, SSP_SS#n (output) falling edge to

first SSP_SCK (output) rising edge

TSSP_SCK-8

TSSP_SCK-2

TD2

Delay time, SSP_SCK (output) falling edge to

MOSI (output) transition

-4.64

12.4

TD3

Delay time, SSP_SCK (output) rising edge to

SSP_SS#n (output) rising edge

TSSP_SCK + 2 TSSP_SCK +8

DATA

MSB IN

LSB IN

LSB OUT

DATA

MSB OUT

SSP_SS#n

SSP_SCK

(SPO=1)

SSP_MISO

(input)

SSP_MOSI

(output)

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