SPEAR1340 datasheet(181/200 Pages) STMICROELECTRONICS

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SPEAr1340

Timing characteristics

Doc ID 023063 Rev 4

181/200

5.15

SSP timing characteristics

This section describes the timing characteristics of the synchronous serial port.

The timing characterization is performed assuming an input transition of 2 ns on all the

inputs and an output load capacitance of 10 pF on all outputs and using PLL1 as the clock

source for the timing extraction.

Note:

The characterization of the SSP has been done using the SPI protocol.

Figure 42.

SSP_SCK waveform

The clock polarity parameter (SPO) indicates the state of the clock signal when it is idle.

This can be programmed in the SSPCR0 register (refer to RM0089, Reference

manual, SPEAr1340 address map and registers).

TCSf

Min and max delay of falling edge of SMI_CLK to

falling edge of SMI_CS0n and SMI_CS1n

0.75

9.60

TCSr

Min and max delay of rising edge of SMI_CLK to

rising edge of SMI_CS0n and SMI_CS1n (1)

0.75+THCLK 9.60+THCLK

THCLK is the period of the programmable HCLK clock

Table 94.

SMI timing characteristics (continued)

Symbol

Description

Min

Max

Unit

SPO= 0

The clock idle state is low.

SPO= 1

The clock idle state is high.

TSSP_SCK(H)

TSSP_SCK

SSP_SCK

(SPO=0)

SSP_SCK

(SPO=1)

TSSP_SCK(L)

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