SPEAR1340 datasheet(178/200 Pages) STMICROELECTRONICS

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Timing characteristics

SPEAr1340

178/200

Doc ID 023063 Rev 4

The setup time is calculated considering:

●

maximum error = 235 ps

●

maximum data skew = 30 ps

Ts calculation formula

Ts= Tclk/4–data_skew –max_error= 469 ps – 30 ps – 235 ps= 204 ps

The hold time, instead, is calculated considering:

●

maximum error = 0 ps

●

maximum data skew = 30 ps

Th calculation formula

Th= Tclk/4–data_skew + max_error= 469 ps – 30 ps + 0 ps= 439 ps

Figure 39.

DQS strobe and DQ/DM signals timing waveform

Read DQS and DQ timing characteristics

The DDR PHY is a sampling-based architecture; this means that the incoming DQS and DQ

signals are sampled by each of the eight dll_clocks. DM signals are not used for reading.

For DQS strobe, a pattern of “000111” is used to detect a rising edge and a pattern of

“111000” is used to detect a falling edge. The maximum error to detect these edges is 1/8

Tclk.

The incoming DQ data is sampled, then the sampled data is analyzed in a window of 4

sampled bits relative to detected DQS edges. The maximum skew, without the contribution

of the pads, between the DQ signals in a single data slice is about 20 ps.

For a frequency of 533.3 MHz, the period of the clock is TCLK= 1.875 ns.

Table 91.

DQ/DM signals timing characteristics

Symbol

Description

Value

Unit

TCLK

Mem_clk period

1.875

Setup time for DQ/DM receive data

204

Hold time for DQ/DM receive data

439

DQS

DQ/DM

Ideal position

max

error

data skew

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