SPEAR1340 datasheet(175/200 Pages) STMICROELECTRONICS

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SPEAr1340

Timing characteristics

Doc ID 023063 Rev 4

175/200

Figure 36.

MCIF - CF true IDE UDMA mode waveform

5.12

MPMC timing characteristics

This section describes the timing characteristics for the multiport DDR controller. The DDR

interface is designed to support the following standards:

●

DDR3-800 and DDR3-1066 standards, as defined in the JESD79-3E JEDEC standard.

●

All DDR2 standards: DDR2-1066, DDR2-800, DDR2-667, DDR2-533, DDR2-400.

Note:

For more information on JEDEC standards, refer to JEDEC Website: www.jedec.org.

This section provides the timing specifications for DDR3 and for DDR2.

For DDR3 the timing values reported below can been obtained only upon successfully

completing the procedure of leveling. Leveling is mandatory for the fly-by topology used for

SDRAM cuts on the PCB. The fly-by topology for the commands, addresses, control signals,

and clocks allows better signal integrity.

For DDR2 you have to use a T branch topology and you have to calibrate the board without

the support of the leveling.

The DDR PHY is an 8-clock sampling-based architecture. The eight clocks are equally

delayed across a clock period equal to the PHY’s core clock. The clocks are generated from

dedicated internal DLLs (dll_clocks).

Table 89.

TrueIDE Ultra DMA timing characteristics

Symbol

Item

Min

Max

Unit

tDH

Data hold time

(from STROBE

edge until data become invalid)

tDS

Data setup time (

the time from data

valid until STROBE edge)

2*T

tCYC

Cycle time

(the time from STROBE

edge to STROBE edge)

>tDH+tDS=3*T

t2CYC

Two cycle times (

the time from

rising edge to next rising edge or

from falling edge to next falling

edge of STROBE)

2*tCYC>6*T

MCIF_DATA[15:0]

t2CYC

MCIF_nIORD_nRE

(STROBE)

tCYC

tDH

tDS

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