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SPEAR1340 Datasheet(PDF) 173 Page - STMicroelectronics |
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SPEAR1340 Datasheet(HTML) 173 Page - STMicroelectronics |
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173 / 200 page ![]() SPEAr1340 Timing characteristics Doc ID 023063 Rev 4 173/200 tCLKlow MCIF_ADDR1_CLE_CLK pulse low tCLK/2-1 – ns tD MCIF_ADDR1_CLE_CLK to MCIF_OUT output delay 20.1 25.9 ns ts Setup time for MCIF_IN data 14 ns th Hold time for MCIF_IN data 0 ns Table 86. MCIF - MMC High speed mode timing characteristics Symbol Description Min Max Unit tCLK MCIF_ADDR1_CLE_CLK clock period 20 – ns tCLKhigh MCIF_ADDR1_CLE_CLK pulse high tCLK/2-1 – ns tCLKlow MCIF_ADDR1_CLE_CLK pulse low tCLK/2-1 – ns tD MCIF_ADDR1_CLE_CLK to MCIF_OUT output delay 0.2 6.1 ns ts Setup time for MCIF_IN data 14 ns th Hold time for MCIF_IN data 1.3 ns Table 87. MCIF - MMC Full speed mode timing characteristics Symbol Description Min Max Unit tCLK MCIF_ADDR1_CLE_CLK clock period 40 – ns tCLKhigh MCIF_ADDR1_CLE_CLK pulse high tCLK/2-1 – ns tCLKlow MCIF_ADDR1_CLE_CLK pulse low tCLK/2-1 – ns tD MCIF_ADDR1_CLE_CLK to MCIF_OUT output delay 20.1 25.9 ns ts Setup time for MCIF_IN data 14 ns th Hold time for MCIF_IN data 0 ns Table 85. MCIF - SD/SDIO Full speed mode timing characteristics (continued) Symbol Description Min Max Unit |
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