SPEAR1340 datasheet(177/200 Pages) STMICROELECTRONICS

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SPEAr1340

Timing characteristics

Doc ID 023063 Rev 4

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Figure 37.

ADDR/CTRLsignals timing waveform

Write DQS timing characteristics

The DDR3 SDRAM supports a write-leveling feature to allow the controller to compensate

the skew between the mem_clk and the data strobe (DQS) at each memory cut. During the

write leveling phase, the controller uses the feedback from the DDR3 SDRAM to adjust the

DQS to mem_clk relationship. The DQS delay established through this procedure helps to

ensure tDQSS specifications in systems using a fly-by topology by deskewing the trace

length mismatch. Based on the 8-phase PHY architecture, the DQS signal is derived from

one of the eight dll_clocks, so it is adjustable with a minimum step of 1/8 of the clock period

(max_error). The sampled value coming from the memory is processed so that the tDQSS

value can vary from 0 to 1/8 Tclk (see Figure 38).

For the DDR2 you have to find the right alignment without the write-leveling support.

Figure 38.

DQS strobe timing waveform

Write DQ/DM timing characteristics

Similar to the creation of the write DQS signal, the write DQ/DM signals are created through

a clock derived from one of the eight dll_clocks.

The clock generating DQ/DM signals should always be set two phases before the clock

generating DQS. This would ensure a 90-degree phase difference between DQ and DQS.

Due to the path delay difference between DQ and DQS, the maximum error respect to the

ideal case is one phase off, so the max error is 1/8 Tclk.

The maximum skew among the DQ/DM signals in a single data slice is about 30 ps.

For a frequency of 533.3 MHz, the period of the clock is TCLK= 1.875 ns.

mem_clk

ADDR/CTRL

max

error

max

error

skew

mem_clk

DQS

tDQSS

SPEAR1340 Datasheet(PDF) 177 Page - STMicroelectronics