JS28F512P30TFA datasheet(41/86 Pages) MICRON

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Datasheet

Sept 2012

Order Number:208042-0

P30-65nm

11.2.9

Burst Length (RCR[2:0])

The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst

reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or

continuous word.

Continuous burst accesses are linear only, and do not wrap within any word length

boundaries (see Table 17, “Burst Sequence Word Ordering” on page 40). When a burst

cycle begins, the device outputs synchronous burst data until it reaches the end of the

“burstable” address space.

11.3

One-Time Programmable (OTP) Registers

The device contains 17 OTP Registers that can be used to implement system security

measures and/or device identification. Each OTP Register can be individually locked.

The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower

64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit

number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers,

are blank. Users can program these registers as needed. Once programmed, users can

then lock the OTP Register(s) to prevent additional bit programming (see Figure 13,

“OTP Register Map” on page 42).

Each OTP Register has an associated Lock Register bit. When a Lock Register bit is

programmed, the associated OTP Register can only be read; it can no longer be

programmed. Each OTP Register can be accessed multiple times to program individual

bits, as long as the register remains unlocked. Additionally, because the Lock Register

bits themselves are OTP, when programmed, Lock Register bits cannot be erased.

Therefore, when a OTP Register is locked, it cannot be unlocked.

JS28F512P30TFA Datasheet(PDF) 41 Page - Micron Technology