JS28F512P30TFA datasheet(43/86 Pages) MICRON

43 / 86 page

Datasheet

Sept 2012

Order Number:208042-0

P30-65nm

The device programs the 64-bit and Sixteen 128-bit user-programmable OTP Register

data 16 bits at a time (see Figure 37, “OTP Register Programming Flowchart” on

page 79). Issuing the OTP Register Program Setup command outside of the OTP

locked OTP Register causes a program error (SR.4 set) and a lock error (SR.1 set).

Note:

When programming the OTP bits in the OTP Registers for a Top Parameter Device, the

upper addresses A[Max:17] must also be driven high (VIH) for TSOP and Easy BGA

packages.

11.3.3

Locking the OTP Registers

Each OTP Register can be locked by programming its respective lock bit in the Lock

issuing the Lock Register Program Setup command, followed by the desired Lock

physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1.

These addresses are used when programming the Lock Registers (see Table 8, “Device

Identifier Information” on page 22).

Bit 0 of Lock Register 0 is already programmed during the manufacturing process at

Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1

of Lock Register 0 can be programmed by user to the upper half segment of the first

128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to

be left as ‘1’ such that the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each

bit of Lock Register 1 corresponds to a specific 128-bit OTP Register; e.g.,

programming LR1.0 locks the corresponding OTP Register 1.

Caution:

After being locked, the OTP Registers cannot be unlocked.

JS28F512P30TFA Datasheet(PDF) 43 Page - Micron Technology