AD9920ABBCZ datasheet(32/112 Pages) AD

32 / 112 page

AD9920A

Rev. B | Page 32 of 112

VERTICAL TIMING GENERATION

The AD9920A provides a flexible solution for generating vertical

CCD timing and can support multiple CCDs and different system

architectures. The vertical transfer clocks are used to shift each

line of pixels into the horizontal output register of the CCD. The

AD9920A allows these outputs to be individually programmed

into various readout configurations by using a four-step process.

Figure 41 shows an overview of how the vertical timing is

generated in four steps.

The individual pulse patterns for XV1 to XV24 are created

by using the vertical pattern group registers.

The V-pattern groups are used to build the V-sequences

where additional information is added.

The readout for an entire field is constructed by dividing

the field into regions and then assigning a sequence to each

region. Each field can contain up to nine different regions

to accommodate the various steps of the readout, such as

high speed line shifts and unique vertical line transfers.

The total number of V-patterns, V-sequences, and fields is

programmable but limited by the number of registers.

The mode registers allow the different fields to be combined

in any order for various readout configurations.

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 3: USE V-SEQUENCE 0

REGION 4: USE V-SEQUENCE 2

XV1

XV2

XV23

XV24

XV1

XV2

XV3

FIELD1

FIELD2

FIELD3

REGION 2: USE V-SEQUENCE 3

FIELD1

FIELD2

FIELD3

FIELD4

FIELD5

FIELD1

FIELD4

FIELD2

XV3

XV23

XV24

VPAT0

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

VPAT1

CREATE THE VERTICAL PATTERN GROUPS,

UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.

BUILD THE V-SEQUENCES BY ADDING START POLARITY,

LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,

GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.

V-SEQUENCE 0

(VPAT0, 1 REP)

V-SEQUENCE 1

(VPAT1, 2 REP)

V-SEQUENCE 2

(VPAT1, N REP)

BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS

AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH

(MAXIMUM OF NINE REGIONS IN EACH FIELD).

USE THE MODE REGISTERS TO CONTROL WHICH FIELDS

ARE USED AND IN WHAT ORDER (MAXIMUM OF SEVEN

FIELDS CAN BE COMBINED IN ANY ORDER).

Figure 41. Summary of Vertical Timing Generation

AD9920ABBCZ Datasheet(PDF) 32 Page - Analog Devices

AD9920ABBCZ Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL