AD9920ABBCZ datasheet(48/112 Pages) AD

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AD9920A

Rev. B | Page 48 of 112

Vertical Sensor Gate (Shift Gate) Patterns

In an interline CCD, the vertical sensor gate (VSG) pulses are

used to transfer the pixel charges from the light-sensitive image

area into light-shielded vertical registers. From the light-shielded

vertical registers, the image is clocked out line-by-line using the

vertical transfer pulses (XV signals) in conjunction with the high

speed horizontal clocks. The AD9920A has 24 vertical signals,

and each signal can be assigned as a VSG pulse instead of as an

XV pulse.

Table 21 summarizes the VSG control registers, which are

mainly located in the field register space (see Table 19). The

VSGSELECT register (Address 0x1C in the fixed address space)

determines which vertical outputs are assigned as VSG pulses.

When a signal is selected to be a VSG pulse, only the starting

polarity and two of the V-pattern toggle positions are used. The

VSGPATSEL register in the V-sequence registers is used to assign

either TOG1 and TOG2 or TOG3 and TOG4 to the VSG signal.

Note that only two of the four V-pattern toggle positions are

available when a vertical signal is selected to be a VSG pulse.

The SGACTLINE1 and SGACTLINE2 registers are used to

select which line in the field is the VSG line. The VSG active

line location is used to reference when the substrate clocking

(SUBCK) signal begins to operate in each field. For more infor-

mation, see the Substrate Clock Operation (SUBCK) section.

Also located in the field registers, the SGMASK register selects

which individual VSG pulses are active in a given field. Therefore,

all SG patterns to be preprogrammed into the V-pattern registers

and the appropriate pulses for the different fields can be enabled

separately.

The AD9920A is an integrated AFETG and V-driver, so the

connections between the AFETG and V-driver are fixed, as

shown in Figure 65 and Figure 66. The VSGSELECT register

must be programmed to 0xFF8000.

Table 21. VSG Control Registers (also see Field Registers in Table 19)

Length (Bits)

Range

Description

VSGSELECT

(Located in Fixed

Address Space, 0x1C)

High/low

Selection of VSG signals from XV signals. Set to 1 to make signal a VSG.

The recommended setting for this register is 0xFF8000.

Bit 0: XV1 selection (0 = XV pulse; 1 = VSG pulse).

Bit 1: XV2 selection.

Bit 23: XV24 selection.

VSGPATSEL

High/low

When VSG signal is selected using the VSGSELECT register, VSGPATSEL

selects which V-pattern toggle positions are used. When this register is

set to 0, Toggle 1 and Toggle 2 are used. When this register is set to 1,

Toggle 3 and Toggle 4 are used.

Bit 0: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).

Bit 1: XV2 selection.

Bit 23: XV24 selection.

SGMASK

High/low, each VSG

Set high to mask each individual VSG output.

Bit 0: XV1 mask.

Bit 23: XV24 mask.

SGACTLINE1

0 to 8191 line number

Selects the line in the field where the VSG signals are active.

SGACTLINE2

0 to 8191 line number

Selects a second line in the field to repeat the VSG signals. If this register

is not used, set it equal in value to SGACTLINE1 or to the maximum value.

VSG PATTERN

PROGRAMMABLE SETTINGS FOR EACH PATTERN:

1START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS).

2FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS).

3SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS).

4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS).

Figure 60. Vertical Sensor Gate Pulse Placement

AD9920ABBCZ Datasheet(PDF) 48 Page - Analog Devices

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