AD9920ABBCZ datasheet(38/112 Pages) AD

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AD9920A

Rev. B | Page 38 of 112

If only two groups are needed (up to eight toggle positions) for

the specified timing, the VPATSELB, VPATSELC, and VPATSELD

registers can be programmed to the same value. If only three

groups are needed, VPATSELC and VPATSELD can be

programmed to the same value. Following this approach

conserves register memory if the four separate V-patterns are

not needed.

Note that when CONCAT_GRP is enabled, the Group A

settings are used only for start position, polarity, length, and

repetitions. All toggle positions for Group A, Group B, Group C,

and Group D are combined together and applied using the

settings in the VSTARTA, VPOL, VLENA, and VREPA registers.

Special Vertical Sequence Alternation (SVSA) Mode

The AD9920A has additional flexibility for combining four

different V-pattern groups in a random sequence that can be

programmed for specific CCD requirements. This mode of

operation allows custom vertical sequences for CCDs that

require more complex vertical timing patterns. For example,

using the special vertical sequence alternation mode, it is

possible to support random pattern concatenation, with

additional support for odd/even line alternation.

Figure 47 illustrates four common and repetitive vertical pattern

segments, A through D, that are derived from the complete

vertical pattern. Figure 48 illustrates how each group can be

concatenated together in an arbitrary order.

To enable the SVSA mode, write the VSEQALT_EN bit,

Address 0x00, Bit 6 in the V-sequence registers, equal to 0x01.

This enables the FREEZE/RESUME registers to function as

VALTSEL registers.

To create SVSA timing, divide the complete vertical timing

pattern into four common and repetitive segments. Identify the

related segments as VPATA, VPATB, VPATC, or VPATD. Up to

four toggle positions for each segment can be programmed using

the V-pattern registers.

Table 16 shows how the segments are specified using a 2-bit

representation. Each bit from VALTSEL0 and VALTSEL1 is

combined to produce four values, corresponding to Pattern A,

Pattern B, Pattern C, and Pattern D.

Table 16. VALTSEL Bit Settings for Even and Odd Lines

Parameter

VALTSEL Bit Settings

VALTSEL0_EVEN

VALTSEL1_EVEN

VALTSEL0_ODD

VALTSEL1_ODD

Resulting Pattern for Even Lines

Resulting Pattern for Odd Lines

When the entire pattern is divided, program VALTSEL0 (even

and odd), Bits[17:0] and VALTSEL1 (even and odd), Bits[17:0]

so that the segments are concatenated in the desired order. If

separate odd and even lines are not required, set the odd and

even registers to the same value.

Figure 49 illustrates the process of using six vertical pattern

segments that are concatenated into a small, merged pattern.

Program the register VREPA_1 to specify the number of segments

that are concatenated into each merged pattern. The maximum

number of segments that can be concatenated to create a merged

pattern is 18. Program VLENA, VLENB, VLENC, and VLEND

to be of equal length. Finally, program HBLK to generate the

proper H-clock timing using the procedure described in the

HBLK Mode 1 Operation section.

It is important to note that because the FREEZE/RESUME registers

are used to specify the VALTSEL registers, it is impossible to use

both the FREEZE/RESUME functions and the SVSA mode.

Table 17. VALTSEL Register Locations

Function of FREEZE/

RESUME Registers When

VSEQALT_EN = 1

VALTSEL0_EVEN, Bits[12:0]

VSEQ register FREEZE1, Bits[12:0]

VALTSEL0_EVEN, Bits[17:13]

VSEQ register RESUME1, Bits[17:13]

VALTSEL1_EVEN, Bits[12:0]

VSEQ register FREEZE2, Bits[12:0]

VALTSEL1_EVEN, Bits[17:13]

VSEQ register RESUME2, Bits[17:13]

VALTSEL0_ODD, Bits[12:0]

VSEQ register FREEZE3, Bits[12:0]

VALTSEL0_ODD, Bits[17:13]

VSEQ register RESUME3, Bits[17:13]

VALTSEL1_ODD, Bits[12:0]

VSEQ register FREEZE4, Bits[12:0]

VALTSEL1_ODD, Bits[17:13]

VSEQ register RESUME4, Bits[17:13]

AD9920ABBCZ Datasheet(PDF) 38 Page - Analog Devices

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