AD9920ABBCZ datasheet(86/112 Pages) AD

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AD9920A

Rev. B | Page 86 of 112

STANDBY MODE OPERATION

The AD9920A contains three standby modes to optimize the

overall power dissipation in a particular application. Bits[1:0]

of Address 0x00 control the power-down state of the device.

Table 48. Power States Set by Standby Register

Standby Register,

Bits[1:0]

Description

Normal operation (full power)

Standby1 mode

Standby2 mode

Standby3 mode (lowest power)

Table 49 and Table 50 summarize the operation of each power-

down mode. The OUT_CONTROL register takes priority over

the Standby1 and Standby2 modes in determining the digital

output states, but Standby3 mode takes priority over OUT_

CONTROL. Standby3 has the lowest power consumption and

even shuts down the crystal oscillator circuit between CLI and

CLO. Therefore, if CLI and CLO are being used with a crystal

to generate the master clock, this circuit is powered down, and

there is no clock signal.

When returning from Standby3 mode to normal operation, the

timing core must be reset at least 500 μs after the STANDBY

circuit to settle.

The vertical outputs can also be programmed to hold a specific

value during the Standby3 mode by using Address 0x26. This

required by the V-driver and CCD to prevent damage when VH

and VL areas are applied. The polarities for Standby1 mode and

Standby2 mode are also programmable, using Address 0x25, and

OUT_CONTROL = low uses the same polarities programmed

for Standby1 and Standby2 modes in Address 0x25. The GPO

polarities are programmable using Address 0x27.

Note that the GPO outputs are high-Z by default at power-up

until Address 0x7A is used to select them as outputs.

CLI FREQUENCY CHANGE

If the input clock CLI is interrupted or changed to a different

frequency, the timing core must be reset for proper operation.

After the CLI clock has settled to the new frequency, or the

previous frequency is resumed, write 0 and then 1 to the

TGCORE_RST register (Address 0x14). This guarantees

that the timing core operates properly.

Table 49. Standby Mode Operation for HCLKMODE = 0x1, 0x2, or 0x4

(Standby Polarities for XV, XSUBCK, and GPO Outputs Are Programmable)

I/O Block

Standby3 (Default)1, 2

OUT_CONTROL = Low2

Standby23, 4

Standby13, 4

AFE

Off

No change

Off

Only REFT, REFB on

Timing Core

Off

No change

Off

CLO Oscillator

Off

No change

Off

CLO

Low

No change

Low

Running

High-Z

Low

Low (4.3 mA)

High-Z

High

High (4.3 mA)

High-Z

Low

Low (4.3 mA)

High-Z

High

High (4.3 mA)

High-Z

Low

Low (4.3 mA)

High-Z

High

High (4.3 mA)

High-Z

Low

Low (4.3 mA)

High-Z

High

High (4.3 mA)

High-Z

Low

Low (4.3 mA)

High-Z

Low

Low (4.3 mA)

Low

VDHDPOL value

Running

Low

VDHDPOL value

Running

DCLK

Low

Running

Low

Running

D0 to D11

Low

XV1 to XV24

Low

XSUBCK

Low

GPO1 to GPO4,

GPO7, and GPO8

Low

1 To exit Standby3 or Standby2 mode, write 00 to the standby register (Address 0x00, Bits[1:0]) and then reset the timing core after 500 μs to guarantee proper settling of the

oscillator and external crystal.

2 Standby3 mode takes priority over OUT_CONTROL for determining the output polarities.

3 These polarities assume OUT_CONTROL = high because OUT_CONTROL = low takes priority over Standby1 and Standby2.

4 Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).

AD9920ABBCZ Datasheet(PDF) 86 Page - Analog Devices

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