AD9920ABBCZ datasheet(60/112 Pages) AD

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AD9920A

Rev. B | Page 60 of 112

XSUBCNT

SUBCK

XSUBCK

VMM

VLL

Figure 80. XSUBCNT, XSUBCK, and SUBCK Output Polarities

V-DRIVER SLEW RATE CONTROL

SUBSTRATE CLOCK OPERATION (SUBCK)

The AD9920A allows the user to moderate the slew rates of the

V-driver outputs when transitioning to VM and VL (this feature

does not affect transitions to VH). This feature minimizes cou-

pling from V-driver activity that occurs while the AD9920A is

clocking valid image pixel data out of the CCD.

The CCD image exposure time is controlled by the substrate

clock signal (SUBCK), which pulses the CCD substrate to clear

out accumulated charge. The AD9920A supports three types of

electronic shuttering: normal, high precision, and low speed.

Along with the SUBCK pulse placement, the AD9920A can

accommodate different readout configurations to further

suppress the SUBCK pulses during multiple field readouts.

There are both coarse and fine mechanisms for controlling the

slew rate of the V1A to V13 outputs. If SRSW = VDD and

SRCTL = VDD, the V1A to V13 switches have roughly 10%

of their normal drive strength (that is, when SRSW = VSS).

If SRSW = VDD and SRCTL < VDD, the voltage applied to

SRCTL controls the slew rate for V1A to V13 transitions from

VM to VL and from VL to VM. For values from 800 mV to

VDD, V1A to V13 transition at a fraction of their maximum

slew rate that is roughly proportional to the voltage applied to

SRCTL. (It is not recommended that voltages less than 800 mV

be applied to SRCTL.)

The SUBCK signal is a programmable string of pulses, each

occupying a line following the primary sense gate active line,

SGACTLINE1 (see Table 43). The SUBCK signal has program-

mable pulse width, line placement, and number of pulses to

accurately control the exposure time.

SUBCK Normal Operation

By default, the AD9920A operates in the normal SUBCK

configuration, in which the SUBCK signal is pulsing in every

VD field (see Figure 81). The SUBCK pulse occurs once per

line, and the total number of repetitions within the field

determines the length of the exposure time. The SUBCK

pulse polarity and toggle positions within a line are program-

mable using the SUBCK_POL and SUBCK_TOG1 registers

(see Table 43). The number of SUBCK pulses per field is

programmed in the SUBCKNUM register (Address 0x75).

The user must tune this voltage for the specific system to

determine the optimal setting that ensures maximum charge

transfer efficiency and minimizes any coupling from V-driver

activity into the image. V14, V15, and V16 are permanently

weak compared with V1A to V13 and are not affected by the

slew rate control function. Note that the slew rate control

feature is intended only for use with CCDs that require V-driver

activity outside the normal horizontal clock blanking region.

As shown in Figure 81, the SUBCK pulses always begin in the line

following the SG active line, which is specified in the SGACTLINE

registers for each field. The SUBCK_POL, SUBCK_TOG1,

SUBCK_TOG2, SUBCKNUM, and SUBCKSUPPRESS registers

are updated at the start of the line after the sensor gate line, as

described in the Updating New Register Values section.

SHUTTER TIMING CONTROL

The AD9920A supports the generation of electronic shuttering

(SUBCK) and also features flexible general-purpose outputs

(GPOs) to control mechanical shuttering, CCD substrate bias

switching, and strobe circuitry. In the following sections, the

terms sense gate (SG) and vertical sense gate (VSG) are used

interchangeably.

AD9920ABBCZ Datasheet(PDF) 60 Page - Analog Devices

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