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CS89712 Datasheet(PDF) 70 Page - Cirrus Logic |
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CS89712 Datasheet(HTML) 70 Page - Cirrus Logic |
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70 / 170 page  CS89712 70 DS502PP2 0x8000.0780 UMSEOI — WR — Write to clear UART modem status changed inter- rupt. 0x8000.07C0 COEOI — WR — Write to clear CODEC sound interrupt. 0x8000.0800 HALT — WR — Write to enter the Idle State. 0x8000.0840 STDBY — WR — Write to enter the Standby State. 0x8000.0880– 0x8000.0FFF Reserved Write will have no effect, read is undefined. 0x8000.1000 FBADDR 0xC RW 4 LCD frame buffer start address. 0x8000.1100 SYSCON2 0 RW 16 System control register 2. 0x8000.1140 SYSFLG2 0 RD 24 System status register 2. 0x8000.1240 INTSR2 0 RD 16 Interrupt status register 2. 0x8000.1280 INTMR2 0 RW 16 Interrupt mask register 2. 0x8000.12C0– 0x8000.147F Reserved Write will have no effect, read is undefined. . 0x8000.1480 UARTDR2 0 RW 16 UART2 Data register. 0x8000.14C0 UBLCR2 0 RW 32 UART2 bit rate and line control register. 0x8000.1500 SS2DR 0 RW 16 Master / slave SSI2 data register. 0x8000.1600 SRXEOF — WR — Write to clear RX FIFO overflow flag. 0x8000.16C0 SS2POP — WR — Write to pop SSI2 residual byte into RX FIFO. 0x8000.1700 KBDEOI — WR — Write to clear keyboard interrupt. 0x8000.1800 Reserved — WR — Do not write to this location. A write will cause the processor to go into an unsupported power state. 0x8000.1840– 0x8000.1FFF Reserved — Write will have no effect, read is undefined. 0x8000.2000 DAIR 0 RW 32 DAI control register. 0x8000.2040 DAIR0 0 RW 32 DAI data register 0. 0x8000.2080 DAIDR1 0 RW 32 DAI data register 1. 0x8000.20C0 DAIDR2 0 WR 21 DAI data register 2. 0x8000.2100 DAISR 0 RW 32 DAI status register. 0x8000.2200 SYSCON3 0 RW 16 System control register 3. 0x8000.2240 INTSR3 0 RD 32 Interrupt status register 3. 0x8000.2280 INTMR3 0 RW 8 Interrupt mask register 3. 0x8000.22C0 LEDFLSH 0 RW 7 LED Flash register. Address Name Default RD/WR Size Comments Table 31. CS89712 Internal Registers (Little Endian Mode) (Continued) Big Endian Mode Name Default RD/WR Size Comments 0x8000.0003 PADR 0 RW 8 Port A Data register Table 32. CS89712 Internal Registers (Big Endian Mode) |
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