CS89712 datasheet(27/170 Pages) CIRRUS

27 / 170 page

CS89712

DS502PP2

of the CS89712’s data bus. Only word (i.e., 4-byte)

and single-byte accesses are supported, and the slot

field is hardcoded to 11, since the slot field is de-

fined as a ‘Reserved field’ by the CL-PS6700. The

chip selects are used to select the device to be ac-

cessed. The space field is made directly from the

A26 and A27 CPU address bits, according to the

decode shown in Table 18. The size field is forced

to 11 if a word access is required, or to 00 if a byte

access is required. This avoids the need to config-

ure the interface after a reset. On the second clock

cycle, the remaining 16 bits of the PC Card address

are multiplexed out onto the lower 16 bits of the

data bus. If the transaction selected is a CL-PS6700

suming there is space available in the CL-PS6700’s

internal write buffer) then the access will continue

on the following two clock cycles. During these

following two clock cycles the upper and lower

halves of the word to be read or written will be put

onto the lower 16 bits of the main data bus.

The ‘ptype’ signal on the CL-PS6700s should be

connected to the CS89712’s WRITE output pin.

During PC Card accesses, the polarity of this pin

changes, and it becomes low to signify a write and

high to signify a read. It is valid with the first half

word of the address. During the second half word

of the address, it is always forced high to indicate

to the CL-PS6700 that the CS89712 has initiated

either the write or read.

The PRDY signals from each of the two CL-

PS6700 devices are connected to Port B bits 0 and

1, respectively. When the PC CARD1 or PC

CARD2 control bits in the SYSCON2 register are

de-asserted, these port bits are available for GPIO.

When asserted, these port bits are used as the

PRDY signals. When the PRDY signal is de-assert-

ed (i.e., low), it indicates that the CL-PS6700 is

busy accessing its card. If a PC CARD access is at-

tempted while the device is busy, the PRDY signal

will cause the CS89712’s CPU to be stalled. The

CS89712’s CPU will have to wait for the card to

become available. DMA transfers to the LCD can

still continue in the background during this period

of time (as described below). The CS89712 can ac-

cess the registers in the CL-PS6700, regardless of

the state of the PRDY signal. If the CS89712 needs

to access the PC CARD via the CL-PS6700, it

waits until the PRDY signal is high before initiat-

ing a transfer request. Once a request is sent, the

PRDY signal indicates if data is available.

In the case of a PC Card write, writes can be posted

to the CL-PS6700 device, with the same timing as

CL-PS6700 internal register writes. Writes will

normally be completed by the CL-PS6700 device

independent of the CS89712 processor activity. If a

posted write times out, or fails to complete for any

other reason, then the CL-PS6700 will issue an in-

terrupt (i.e., a WR_FAIL interrupt). In the case

where the CL-PS6700 write buffer is already full,

the PRDY signal will be de-asserted (i.e., driven

low) and the transaction will be stalled pending an

available slot in the buffer. In this case, the

CS89712’s CPU will be stalled until the write can

Space Field Value

PC CARD Memory Space

Attribute

I/O

Common memory

CL-PS6700 registers

Table 18. Space Field Decoding

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