CS89712 datasheet(79/170 Pages) CIRRUS

79 / 170 page

CS89712

DS502PP2

3.4.3

PDDR Port D Data Register (address 0x8000.0003)

Values written to this 8-bit read / write register will be output on Port D pins if the corresponding data direc-

tion bits are set low (port output). Values read from this register reflect the external state of Port D, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.4.4

PADDR Port A Data Direction Register (address 0x8000.0040)

Bits set in this 8-bit read / write register will select the corresponding pin in Port A to become an output, clear-

ing a bit sets the pin to input. All bits are cleared by a system reset.

3.4.5

PBDDR Port B Data Direction Register (address 0x8000.0041)

Bits set in this 8-bit read / write register will select the corresponding pin in Port B to become an output, clear-

ing a bit sets the pin to input. All bits are cleared by a system reset.

3.4.6

PDDDR Port D Data Direction Register (address 0x8000.0043)

Bits cleared in this 8-bit read / write register will select the corresponding pin in Port D to become an output,

setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output by default.

3.4.7

PEDR Port E Data Register (address 0x8000.0080)

Values written to this 3-bit read / write register will be output on Port E pins if the corresponding data direc-

tion bits are set high (port output). Values read from this register reflect the external state of Port E, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.4.8

PEDDR Port E Data Direction Register (address 0x8000.00C0)

Bits set in this 3-bit read / write register will select the corresponding pin in Port E to become an output, while

the clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default.

3.5 System Control Registers

3.5.1

SYSCON1 The System Control Register 1 (address 0x8000.0100)

The system control register is a 21-bit read / write register which controls all the general configuration of the

CS89712, as well as modes etc. for peripheral devices. All bits in this register are cleared by a system reset. The

bits in the system control register SYSCON1 are defined in Table 37.

23:21

17:16

Reserved

IRTXM

WAKEDIS

EXCKEN

ADCKSEL

SIREN

CDENRX

CDENTX

LCDEN

DBGEN

BZMOD

BZTOG

3:0

UART1EN

TC2S

TC2M

TC1S

TC1M

Keyboard scan

CS89712 Datasheet(PDF) 79 Page - Cirrus Logic

CS89712 Datasheet(HTML) 79 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL