CS89712 datasheet(75/170 Pages) CIRRUS

75 / 170 page

CS89712

DS502PP2

Section 3.2.7, “Status/Control Register Summary”

provides a detailed description of each register.

3.2.6.1

Act-Once Bits

There are four bits that cause a certain action only

once when set. These "Act-Once" bits are: Skip_1

(RxCFG register bit 6), RESET (SelfCTL register

bit 6), ResetRxDMA (BusCTL register bit 6), and

SWint-X (BufCFG register bit 6). To cause the ac-

tion again, the software must set the bit again. Act-

Once bits are always read as clear.

3.2.6.2

Temporal Bits

Temporal bits are bits that are set and cleared by the

Ethernet port automatically. This includes all status

bits in the three status registers (LineST, SelfST,

and BusST), the RxDest bit (BufEvent bit F), and

the Rx128 bit (BufEvent bit B). Like all Event bits,

RxDest and Rx128 are cleared when read by the

software.

3.2.6.3

Interrupt Enable Bits and Events

Interrupt Enable bits end with the suffix iE and are

located in three Configuration registers: RxCFG,

TxCFG, and BufCFG. Each Interrupt Enable bit

corresponds to a specific event. If an Interrupt En-

able bit is set and its corresponding event occurs,

the Ethernet port generates an interrupt.

The bits that report when various events occur are

located in three Event registers and two counters.

The Event registers are RxEvent, TxEvent, and

BufEvent. The counters are RxMISS and TxCOL.

Each Interrupt Enable bit and its associated Event

are identified in Table 35.

An Event bit will be set whenever the specified

event happens, whether or not the associated Inter-

rupt Enable bit is set. All Event registers are cleared

upon read-out by the software.

3.2.6.4

Accept Bits

There are nine Accept bits located in the RxCTL

Accept bits indicate which types of frames will be

accepted by the CS89712. Four of these bits have

corresponding Interrupt Enable (iE) bits. An Ac-

cept bit and an Interrupt Enable bit are independent

operations. It is possible to set either, neither, or

both bits. The four corresponding pairs of bits are:

If one of the above Interrupt Enable bits is set and

the corresponding Accept bit is clear, the CS89712

Interrupt Enable Bit

(register name)

Event Bit or Counter

(register name)

ExtradataiE (RxCFG)

Extradata (RxEvent)

RuntiE (RxCFG)

Runt (RxEvent)

CRCerroriE (RxCFG)

CRCerror (RxEvent)

RxOKiE (RxCFG)

RxOK (RxEvent)

16colliE (TxCFG)

16coll (TxEvent)

AnycolliE (TxCFG)

“Number-of Tx-colli-

sions” counter is incre-

mented (TxEvent)

JabberiE (TxCFG)

Jabber (TxEvent)

Out-of-windowiE (TxCFG) Out-of-window (TxEvent)

TxOKiE (TxCFG)

TxOK (TXEvent)

MissOvfloiE (BufCFG)

RxMISS counter over-

flows past 1FFh

TxColOvfloiE (BufCFG)

TxCOL counter overflows

past 1FFh

RxDestiE (BufCFG)

RxDest (BufEvent)

Rx128iE (BufCFG)

Rx128 (BufEvent)

RxMissiE (BufCFG)

RxMISS (BufEvent)

TxUnderruniE (BufCFG)

TxUnderrun (BufEvent)

Rdy4TxiE (BufCFG)

Rdy4Tx (BufEvent)

Table 35. Interrupt Enable Bits and Events

IE Bit in RxCFG

A Bit in RxCTL

ExtradataiE

ExtradataA

RuntiE

RuntA

CRCerroriE

CRCerrorA

RxOKiE

RxOKA

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