CS89712 datasheet(98/170 Pages) CIRRUS

98 / 170 page

CS89712

DS502PP2

generated repetitively at 1/8th the byte transfer rate and the FIFO state can be read in the system flags reg-

ister. The net data transfer rate to / from the codec device is 8 kBytes/s, giving an interrupt rate of 1 kHz.

3.9.6

STFCLR Clear all “Start Up Reason” Flags Location (address 0x8000.05C0)

A write to this location will clear all the “Start Up Reason” flags in the system flags status register SYSFLG.

The ‘Start Up Reason’ flags should first read to determine the reason why the chip was started (i.e., a new

battery was installed). Any value may be written to this location.

3.10 UART Registers

3.10.1

UARTDR1–2, UART1–2 Data Registers (address 0x8000.0480 and 0x8000.1480)

The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the internal UARTs

1 and 2.

Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled. If not it is

stored in a one byte holding register. This write will initiate transmission from the UART.

The UART data read registers are made up of the 8-bit data byte received from the UART together with three bits

of error status. If the FIFO is enabled, data read from this register is popped from the 16 byte data RX FIFO. If the

FIFO is not enabled, it is read from a one byte buffer register containing the last byte received by the UART. If it is

enabled, data received and error status is automatically pushed onto the RX FIFO. The RX FIFO is 10-bits wide by

16 deep.

Note:

These registers should be accessed as words.

7:0

OVERR

PARERR

FRMERR

RX data

Bit

Description

FRMERR: UART framing error. This bit is set if the UART detected a framing error while receiv-

ing the associated data byte. Framing errors are caused by non-matching word lengths or bit

rates.

PARERR: UART parity error. This bit is set if the UART detected a parity error while receiving the

data byte.

OVERR: UART over-run error. This bit is set if more data is received by the UART and the FIFO

is full. The overrun error bit is not associated with any single character and so is not stored in the

FIFO. If this bit is set, the entire contents of the FIFO is invalid and should be cleared. This error

bit is cleared by reading the UARTDR register.

Table 53. UARTDR1-2 UART1-2

CS89712 Datasheet(PDF) 98 Page - Cirrus Logic