CS89712 datasheet(87/170 Pages) CIRRUS

87 / 170 page

CS89712

DS502PP2

16:21

RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last incre-

ment of the RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down

to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.

URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the RX holding register is empty. If the FIFO is enabled, the URXFE bit will be set when the

RX FIFO is empty.

UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the TX holding register is full. If the FIFO is enabled, the UTXFF bit will be set when the TX

FIFO is full.

CRXFE: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty.

CTXFF: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full.

SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in

or out of the synchronous serial interface, when clear data is valid to read.

27:28

BOOTBIT0–1: These bits indicate the default (power-on reset) bus width of the ROM interface.

See

Memory Configuration Registers for more details on the ROM interface bus width. The state

of these bits reflect the state of Port E[0:1] during power on reset, as shown in the table below.

ID: Will always read ‘1’ for the CS89712 device.

30:31

VERID: Version ID bits. These 2 bits determine the version id for the CS89712. Will read ‘10’ for

the initial version.

Bit

Description

Table 40. SYSFLG (Continued)

PE[1]

(BOOTBIT1)

PE[0]

(BOOTBIT0)

Boot option

32-bit

8-bit

16-bit

Reserved

CS89712 Datasheet(PDF) 87 Page - Cirrus Logic