SST26VF032BEUI datasheet(18/76 Pages) MICROCHIP

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SST26VF032BEUI

DS20006152A-page 18

 2019 Microchip Technology Inc.

5.8

SPI Quad I/O Read

The SPI Quad I/O Read (SQIOR) instruction supports

frequencies of up to 104 MHz from 2.7-3.6V and up to

80 MHz from 2.3-3.6V. SST26VF032BEUI requires the

IOC bit in the configuration register to be set to ‘1’ prior

to executing the command. Initiate SQIOR by execut-

ing an 8-bit command, EBH. The device then switches

to 4-bit I/O mode for address bits A[23-0], followed by

the Set Mode configuration bits M[7:0], and two dummy

bytes.CE# must remain active low for the duration of

the SPI Quad I/O Read. See Figure 5-9 for the SPI

Quad I/O Read sequence.

Following the dummy bytes, the device outputs data

from the specified address location. The device contin-

ually streams data output through all addresses until

terminated by a low-to-high transition on CE#. The

internal address pointer automatically increments until

the highest memory address is reached, at which point

the address pointer returns to the beginning of the

address space.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SPI Quad I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another Read com-

mand, EBH, and does not require the op-code to be

entered again. The host may set the next SQIOR cycle

by driving CE# low, then sending the four-bit wide input

for address A[23:0], followed by the Set Mode configu-

ration bits M[7:0], and two dummy cycles. After the two

dummy cycles, the device outputs the data starting

from the specified address location. There are no

restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. See Fig-

ure 5-10 for the SPI Quad I/O Mode Read sequence

when M[7:0] = AXH.

FIGURE 5-9:

SPI QUAD I/O READ SEQUENCE

A20 A16 A12 A8 A4 A0 M4 M0

CE#

SIO0

SCK

012345678

16 17

MODE 3

MODE 0

91011

EBH

20005218 F49.2

b4 b0

SIO1

SIO2

SIO3

Address

Data

Byte 0

Dummy

13 14

20 21

b4 b0

A21 A17 A13 A9 A5 A1 M5 M1

b5 b1 b5 b1

A22 A18 A14 A10 A6 A2 M6 M2

b6 b2 b6 b2

A23 A19 A15 A11 A7 A3 M7 M3

b7 b3 b7 b3

Set

Mode

Data

Byte 1

MSN LSN

X X X X

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

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