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SST26VF032BEUI Datasheet(PDF) 27 Page - Microchip Technology |
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SST26VF032BEUI Datasheet(HTML) 27 Page - Microchip Technology |
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27 / 76 page ![]() 2019 Microchip Technology Inc. DS20006152A-page 27 SST26VF032BEUI 5.20 Page-Program The Page-Program instruction programs up to 256 Bytes of data in the memory, and supports both SPI and SQI protocols. The data for the selected page address must be in the erased state (FFH) before initi- ating the Page-Program operation. A Page-Program applied to a protected memory area will be ignored. Prior to the program operation, execute the WREN instruction. To execute a Page-Program operation, the host drives CE# low then sends the Page Program command cycle (02H), three address cycles followed by the data to be programmed, then drives CE# high. The programmed data must be between 1 to 256 Bytes and in whole Byte increments; sending less than a full Byte will cause the partial Byte to be ignored. Poll the BUSY bit in the Sta- tus register, or wait TPP, for the completion of the inter- nal, self-timed, Write operation. See Figures 5-25 and 5-26 for the Page-Program sequence. When executing Page-Program, the memory range for the SST26VF032BEUI is divided into 256 Byte page boundaries. The device handles shifting of more than 256 Bytes of data by maintaining the last 256 Bytes of data as the correct data to be programmed. If the target address for the Page-Program instruction is not the beginning of the page boundary (A[7:0] are not all zero), and the number of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be pro- grammed at the start of that target page. FIGURE 5-25: PAGE-PROGRAM SEQUENCE (SQI) FIGURE 5-26: PAGE-PROGRAM SEQUENCE (SPI) 20005218 F10.1 MODE 3 0 SCK SIO(3:0) CE# C1 C0 MODE 0 2 A5 A4 MSN LSN 4 A3 A2 6 A1 A0 8 H0 L0 10 H1 L1 12 H2 L2 HN LN Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 255 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble 20005218 F60.1 CE# SO SI SCK ADD. 01 2 3 4 5 6 7 8 ADD. ADD. Data Byte 0 02 HIGH IMPEDANCE 15 16 23 24 31 32 39 MODE 0 MODE 3 MSB MSB MSB LSB CE#(cont’) SO(cont’) SI(cont’) SCK(cont’) 40 41 42 43 44 45 46 47 48 Data Byte 1 HIGH IMPEDANCE MSB MSB MSB LSB 50 51 52 53 54 55 49 Data Byte 2 Data Byte 255 LSB LSB LSB LSB |
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