SST26VF032BEUI datasheet(16/76 Pages) MICROCHIP

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SST26VF032BEUI

DS20006152A-page 16

 2019 Microchip Technology Inc.

5.6

High-Speed Read

The High-Speed Read instruction, 0BH, is supported in

both SPI bus protocol and SQI protocol. This instruc-

tion supports frequencies of up to 104 MHz from 2.7-

3.6V and up to 80 MHz from 2.3-3.6V. On power-up,

the device is set to use SPI.

Initiate High-Speed Read by executing an 8-bit com-

mand, 0BH, followed by address bits A[23-0] and a

dummy byte. CE# must remain active low for the dura-

tion of the High-Speed Read cycle. See Figure 5-6 for

the High-Speed Read sequence for SPI bus protocol.

FIGURE 5-6:

HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

In SQI protocol, the host drives CE# low then send the

Read command cycle command, 0BH, followed by

three address cycles, a Set Mode Configuration cycle,

and two dummy cycles. Each cycle is two nibbles

(clocks) long, most significant nibble first.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The device continually streams

data output through all addresses until terminated by a

low-to-high transition on CE#. The internal address

pointer automatically increments until the highest mem-

ory address is reached, at which point the address

pointer returns to address location 000000H. During

this operation, blocks that are Read-locked will output

data 00H.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SQI High-Speed Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another Read com-

mand, 0BH, and does not require the op-code to be

entered again. The host may initiate the next Read

cycle by driving CE# low, then sending the four-bits

input for address A[23:0], followed by the Set Mode

configuration bits M[7:0], and two dummy cycles. After

the two dummy cycles, the device outputs the data

starting from the specified address location. There are

no restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. While in

the Set Mode configuration, the RSTQIO command will

only return the device to a state where it can accept

new command instruction. An additional RSTQIO is

required to reset the device to SPI mode. See Figure 5-

10 for the SPI Quad I/O Mode Read sequence when

M[7:0] = AXH.

FIGURE 5-7:

HIGH-SPEED READ SEQUENCE (SQI)

20005218 F31.0

CE#

SO/SIO1

SI/SIO0

SCK

ADD.

012 3 4 5 6 7 8

ADD.

HIGH IMPEDANCE

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N+1

MSB

MODE 0

MODE 3

DOUT

71 72

DOUT

Address

Dummy

Command

Data Byte 0

MSN

LSN

Data Byte 7

Mode

20005218 F47.0

SCK

SIO(3:0)

CE#

XH0

913

MODE 3

MODE 0

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

Hx = High Data Nibble, Lx = Low Data Nibble C[1:0]=0BH

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