SST26VF032BEUI datasheet(15/76 Pages) MICROCHIP

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DS20006152A-page 15

SST26VF032BEUI

5.4

Enable Quad I/O (EQIO)

The Enable Quad I/O (EQIO) instruction, 38H, enables

the flash device for SQI bus operation. Upon comple-

tion of the instruction, all instructions thereafter are

expected to be 4-bit multiplexed input/output (SQI

mode) until a power cycle or a “Reset Quad I/O instruc-

tion” is executed. See Figure 5-3.

FIGURE 5-3:

ENABLE QUAD I/O SEQUENCE

5.5

Reset Quad I/O (RSTQIO)

The Reset Quad I/O instruction, FFH, resets the device

to 1-bit SPI protocol operation or exits the Set Mode

configuration during a read sequence. This command

allows the flash device to return to the default I/O state

(SPI) without a power cycle, and executes in either 1-

bit or 4-bit mode. If the device is in the Set Mode con-

figuration, while in SQI High-Speed Read mode, the

RSTQIO command will only return the device to a state

where it can accept new command instruction. An addi-

tional RSTQIO is required to reset the device to SPI

mode.

To execute a Reset Quad I/O operation, the host drives

CE# low, sends the Reset Quad I/O command cycle

(FFH) then, drives CE# high. Execute the instruction in

either SPI (8 clocks) or SQI (2 clocks) command

cycles. For SPI, SIO[3:1] are don’t care for this com-

mand, but should be driven to VIH or VIL. See Figures

5-4 and 5-5.

FIGURE 5-4:

RESET QUAD I/O SEQUENCE (SPI)

FIGURE 5-5:

RESET QUAD I/O SEQUENCE (SQI)

20005218 F43.0

MODE 3

SCK

SIO0

CE#

MODE 0

234567

SIO[3:1]

Note: SIO[3:1] must be driven VIH

20005218 F73.0

MODE 3

SCK

SIO0

CE#

MODE 0

234567

SIO[3:1]

Note: SIO[3:1]

20005218 F74.0

MODE 3

SCK

SIO(3:0)

CE#

MODE 0

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