SST26VF032BEUI datasheet(17/76 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006152A-page 17

SST26VF032BEUI

5.7

SPI Quad-Output Read

The SPI Quad-Output Read instruction supports fre-

quencies of up to 104 MHz from 2.7-3.6V and up to 80

MHz from 2.3-3.6V. SST26VF032BEUI requires the

IOC bit in the configuration register to be set to ‘1’ prior

to executing the command. Initiate SPI Quad-Output

Read by executing an 8-bit command, 6BH, followed

by address bits A[23-0] and a dummy byte. CE# must

remain active low for the duration of the SPI Quad

Mode Read. See Figure 5-8 for the SPI Quad Output

Read sequence.

Following the dummy byte, the device outputs data

from SIO[3:0] starting from the specified address loca-

tion. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal address pointer auto-

matically increments until the highest memory address

is reached, at which point the address pointer returns

to the beginning of the address space.

FIGURE 5-8:

SPI QUAD OUTPUT READ

CE#

SIO0

SCK

012345678

31 32

MODE 3

MODE 0

15 16

6BH

20005218 F48.3

39 40 41

A[23:16]

A[15:8]

A[7:0]

b4 b0

b5 b1

b6 b2

b7 b3

SIO1

SIO2

SIO3

Address

OP Code

Data

Byte 0

Dummy

Data

Byte N

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

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